公开(公告)号：US10083722B2

公开(公告)日：2018-09-25

申请号：US15607699

申请日：2017-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Reum Oh ,  Je-Min Ryu ,  Pavan Kumar Kasibhatla

IPC: G11C5/06 ,  G11C5/02 ,  G06F12/084 ,  G06F12/0893 ,  G11C7/10 ,  G11C29/12 ,  G11C29/48 ,  H01L25/18

CPC classification number: G11C5/02 ,  G06F12/084 ,  G06F12/0893 ,  G11C5/025 ,  G11C7/1006 ,  G11C29/1201 ,  G11C29/48 ,  G11C2207/2245 ,  H01L25/18

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

公开(公告)号：US20180032252A1

公开(公告)日：2018-02-01

申请号：US15617450

申请日：2017-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAK-SOO YU ,  Je-Min Ryu ,  Reum Oh ,  Pavan Kumar Kasibhatla ,  Seok-In Hong

IPC: G06F3/06 ,  G11C5/06 ,  G11C5/02

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

公开(公告)号：US11074961B2

公开(公告)日：2021-07-27

申请号：US16251983

申请日：2019-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US10768824B2

公开(公告)日：2020-09-08

申请号：US16418502

申请日：2019-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Soo Yu ,  Je-Min Ryu ,  Reum Oh ,  Pavan Kumar Kasibhatla ,  Seok-In Hong

IPC: G06F3/06 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

公开(公告)号：US12073871B2

公开(公告)日：2024-08-27

申请号：US18223078

申请日：2023-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/40 ,  G06F15/78 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G06F15/7821 ,  G11C7/1006 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US11749339B2

公开(公告)日：2023-09-05

申请号：US17883498

申请日：2022-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G06F15/7821 ,  G11C7/1006 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US10262699B2

公开(公告)日：2019-04-16

申请号：US16106492

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Reum Oh ,  Je-Min Ryu ,  Pavan Kumar Kasibhatla

IPC: G11C5/02 ,  G11C29/48 ,  G11C29/12 ,  G11C7/10 ,  G06F12/0893 ,  G06F12/084 ,  H01L25/18

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

公开(公告)号：US11790981B2

公开(公告)日：2023-10-17

申请号：US17883498

申请日：2022-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G06F15/7821 ,  G11C7/1006 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US11482278B2

公开(公告)日：2022-10-25

申请号：US17369010

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US20200035291A1

公开(公告)日：2020-01-30

申请号：US16251983

申请日：2019-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/10 ,  G06F15/78

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.