公开(公告)号：US20230236836A1

公开(公告)日：2023-07-27

申请号：US18194174

申请日：2023-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUKHAN LEE ,  SHINHAENG KANG ,  NAMSUNG KIM ,  SEONGIL O ,  HAK-SOO YU

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

CPC classification number: G06F9/30145 ,  G06F9/321 ,  G06F15/7821

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

公开(公告)号：US20180032252A1

公开(公告)日：2018-02-01

申请号：US15617450

申请日：2017-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAK-SOO YU ,  Je-Min Ryu ,  Reum Oh ,  Pavan Kumar Kasibhatla ,  Seok-In Hong

IPC: G06F3/06 ,  G11C5/06 ,  G11C5/02

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

公开(公告)号：US20200294558A1

公开(公告)日：2020-09-17

申请号：US16813851

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD,

Inventor： HAK-SOO YU ,  NAMSUNG KIM ,  KYOMIN SOHN ,  SEONGIL O ,  SUKHAN LEE

IPC: G11C7/10 ,  G11C11/409 ,  G11C11/408 ,  G11C5/02

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

公开(公告)号：US20170344301A1

公开(公告)日：2017-11-30

申请号：US15493292

申请日：2017-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JE MIN RYU ,  REUM OH ,  HAK-SOO YU

IPC: G06F3/06

Abstract: An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.

公开(公告)号：US20150199234A1

公开(公告)日：2015-07-16

申请号：US14595856

申请日：2015-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOJIN CHOI ,  SU-A KIM ,  HAK-SOO YU ,  SEONG-YOUNG SEO ,  MU-JIN SEO

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method of operating a memory device includes: checking for errors in data read from a first address of a memory cell array of the memory device; counting the number of errors that occurred in the data read from the first address; receiving a first command for data read from the first address; determining whether the number of errors that occurred in the data read from the first address is greater than or equal to a first value; and mapping the first address to a second address, if the number of errors that occurred in the data read from the first address is greater than or equal to the first value.

Abstract translation: 操作存储器件的方法包括：检查从存储器件的存储单元阵列的第一地址读取的数据中的错误; 对从第一个地址读取的数据中发生的错误数进行计数; 接收从第一地址读取数据的第一命令; 确定在从所述第一地址读取的数据中发生的错误的数量是否大于或等于第一值; 并且如果从第一地址读取的数据中发生的错误的数目大于或等于第一个值，则将第一地址映射到第二地址。

公开(公告)号：US20220036929A1

公开(公告)日：2022-02-03

申请号：US17504918

申请日：2021-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAK-SOO YU ,  NAMSUNG KIM ,  KYOMIN SOHN ,  SEONGIL O ,  SUKHAN LEE

IPC: G11C7/10 ,  G11C5/02 ,  G11C11/408 ,  G11C11/409

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

公开(公告)号：US20190318230A1

公开(公告)日：2019-10-17

申请号：US16191906

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOO-YEONG CHO ,  SEONG-IL O ,  HAK-SOO YU ,  MIN-SU CHOI

IPC: G06N3/063 ,  G06N3/04

Abstract: Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.