公开(公告)号：US08837246B2

公开(公告)日：2014-09-16

申请号：US13803520

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Heung Kim ,  In Chul Jeong

IPC: G11C7/00 ,  G11C11/402 ,  G11C11/406

CPC classification number: G11C11/402 ,  G11C11/40618

Abstract: A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L.

Abstract translation: 存储器刷新方法包括从存储器件的N个存储体中选择至少一个存储区，以及在刷新周期的L个刷新周期之一中激活包括在所述至少一个存储体中的多个字线中的K个字线。 每个N个组包括M个字线，N，K和M各自是大于或等于2的自然数，L是小于或等于M的自然数，K等于M * N / L。

公开(公告)号：US11194505B2

公开(公告)日：2021-12-07

申请号：US17173754

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C5/02 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

公开(公告)号：US11334282B2

公开(公告)日：2022-05-17

申请号：US17173779

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

公开(公告)号：US08902686B2

公开(公告)日：2014-12-02

申请号：US13833195

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Chul Jeong ,  Ki Heung Kim

IPC: G11C7/00 ,  G11C29/04 ,  G11C29/00

CPC classification number: G11C29/04 ,  G11C29/702 ,  G11C29/808

Abstract: A method of repairing a word line of a memory device includes receiving a row address, comparing a received row address with a row address of a defective cell, enabling a normal word line and a redundant word line, which correspond to the row address, according to a result of the row address comparison, receiving a column address, comparing a received column address with a column address of the defective cell, and performing a memory access operation on one of the normal word line and the redundant word line according to a result of the column address comparison.

Abstract translation: 修复存储器件的字线的方法包括：接收行地址，将接收到的行地址与有缺陷单元的行地址进行比较，使能对应于行地址的正常字线和冗余字线，根据 通过行地址比较的结果，接收列地址，将接收到的列地址与缺陷单元的列地址进行比较，并根据结果对正常字线和冗余字线之一执行存储器访问操作 的列地址比较。

公开(公告)号：US11681457B2

公开(公告)日：2023-06-20

申请号：US17728107

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C7/00 ,  G11C5/04 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0653 ,  G06F3/0655 ,  G06F12/0292 ,  G06F13/1694 ,  G11C7/1057 ,  G11C7/1084

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

公开(公告)号：US10996885B2

公开(公告)日：2021-05-04

申请号：US16208989

申请日：2018-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C5/02 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.