公开(公告)号：US11334282B2

公开(公告)日：2022-05-17

申请号：US17173779

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

公开(公告)号：US11194505B2

公开(公告)日：2021-12-07

申请号：US17173754

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C5/02 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

公开(公告)号：US11681457B2

公开(公告)日：2023-06-20

申请号：US17728107

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C7/00 ,  G11C5/04 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0653 ,  G06F3/0655 ,  G06F12/0292 ,  G06F13/1694 ,  G11C7/1057 ,  G11C7/1084

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

公开(公告)号：US10996885B2

公开(公告)日：2021-05-04

申请号：US16208989

申请日：2018-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C5/02 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.