公开(公告)号：US20250120095A1

公开(公告)日：2025-04-10

申请号：US18802058

申请日：2024-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Lee ,  Geonhui Han ,  Hyunsang Hwang ,  Dongho Ahn ,  Jinmyung Choi

IPC: H10B63/00

Abstract: A semiconductor device includes a substrate, source/drain regions on the substrate, a channel layer between the source/drain regions and including indium gallium zinc oxide (IGZO), a variable resistance layer on the channel layer and including metal oxide that satisfies a stoichiometric ratio of metal to oxygen, a gate insulating layer on the variable resistance layer and including metal oxide that does not satisfy the stoichiometric ratio of metal to oxygen, and a gate electrode on the gate insulating layer.

公开(公告)号：US12254922B2

公开(公告)日：2025-03-18

申请号：US18157408

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo Choi ,  Young Jae Kang ,  Bonwon Koo ,  Yongyoung Park ,  Hajun Sung ,  Dongho Ahn ,  Kiyeon Yang ,  Wooyoung Yang ,  Changseung Lee

IPC: G11C13/00 ,  H10B63/10 ,  H10B63/00

Abstract: A memory device includes a memory cell including a selection layer and a phase change material layer, and a controller, wherein the selection layer includes a switching material, the phase change material layer includes a phase change material, and the controller is configured to apply a write pulse to the selection layer and the phase change material layer and control a polarity, a peak value, and a shape of the write pulse.

公开(公告)号：US20240365567A1

公开(公告)日：2024-10-31

申请号：US18471585

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Lee ,  Dongho Ahn ,  Jin Myung Choi

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A semiconductor device according to an embodiment includes a gate stack structure and a channel structure. The gate stack structure includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on a substrate in a first direction perpendicular to an upper surface of the substrate. The channel structure includes a portion penetrating through the gate stack structure and extending in the first direction. The channel structure includes a channel layer, a resistance change layer, and a metal-containing layer sequentially stacked. The metal-containing layer includes a metal or a metal compound.

公开(公告)号：US11616197B2

公开(公告)日：2023-03-28

申请号：US16988957

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ja Bin Lee ,  Zhe Wu ,  Kwangmin Park ,  Gwangguk An ,  Dongho Ahn ,  Seung-Geun Yu ,  Jinwoo Lee

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.

公开(公告)号：US11037992B2

公开(公告)日：2021-06-15

申请号：US16567094

申请日：2019-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghee Park ,  Dongho Ahn ,  Changyup Park ,  Zhe Wu

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.

公开(公告)号：US20180019281A1

公开(公告)日：2018-01-18

申请号：US15454064

申请日：2017-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ja bin LEE ,  Jeonghee Park ,  Dongho Ahn ,  Zhe Wu ,  Heeju Shin ,  Jinwoo Lee

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2427 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: A variable resistance memory device may include separate memory cells between separate vertical intersections of first conductive lines extending in a first direction and second conductive lines extending in a second direction intersecting the first direction. A memory cell may include a switching element and a variable resistance structure coupled in series between a first conductive line and a second conductive line. The switching element may include at least one insulative impurity and a chalcogenide material. The variable resistance structure may reversibly switch phases, between a crystalline state and an amorphous state, at a first phase transition temperature, and the switching element may reversibly switch phases, between a crystalline state and an amorphous state, at a second phase transition temperature, where the second phase transition temperature is greater than the first phase transition temperature.