公开(公告)号：US11245073B2

公开(公告)日：2022-02-08

申请号：US16944350

申请日：2020-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Geun Yu ,  Zhu Wu ,  Ja Bin Lee ,  Jung Moo Lee ,  Jinwoo Lee ,  Kyubong Jung

IPC: H01L45/00 ,  H01L27/24

Abstract: A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

公开(公告)号：US20210193922A1

公开(公告)日：2021-06-24

申请号：US16988957

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ja Bin Lee ,  Zhe Wu ,  Kwangmin Park ,  Gwangguk An ,  Dongho Ahn ,  Seung-Geun Yu ,  Jinwoo Lee

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.

公开(公告)号：US10777745B2

公开(公告)日：2020-09-15

申请号：US16364232

申请日：2019-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Geun Yu ,  Zhu Wu ,  Ja Bin Lee ,  Jung Moo Lee ,  Jinwoo Lee ,  Kyubong Jung

IPC: H01L45/00 ,  H01L27/24

Abstract: A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

公开(公告)号：US11616197B2

公开(公告)日：2023-03-28

申请号：US16988957

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ja Bin Lee ,  Zhe Wu ,  Kwangmin Park ,  Gwangguk An ,  Dongho Ahn ,  Seung-Geun Yu ,  Jinwoo Lee

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.