公开(公告)号：US12206278B2

公开(公告)日：2025-01-21

申请号：US18297780

申请日：2023-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ku-Chul Jung ,  Chul-Woo Park ,  Sung-Geun Yoon ,  Sang-Hyun Ryu

IPC: H02J7/34 ,  H02J7/00 ,  H02J50/10 ,  H02J50/12 ,  H02J50/80 ,  H04B5/79

Abstract: An apparatus for wired and wireless charging of an electronic device are provided. The electronic device includes a housing, a display on a surface of the housing, a battery mounted in the housing, a circuit electrically connected with the battery, a conductive pattern positioned in the housing, electrically connected with the circuit, and configured to wirelessly transmit power to an external device, a connector on another surface of the housing and electrically connected with the circuit, a memory, and a processor electrically connected with the display, the battery, the circuit, the connector, and/or the memory. The circuit is configured to electrically connect the battery with the conductive pattern to wirelessly transmit power to the external device and electrically connect the battery with the connector to transmit power to the external device by wire, simultaneously or selectively, with wirelessly transmitting power to the external device.

公开(公告)号：US10256653B2

公开(公告)日：2019-04-09

申请号：US15483388

申请日：2017-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Geun Yoon ,  Chul-Woo Park ,  Ku-Chul Jung ,  Hyun-Deok Seo ,  Min-Jeong Lee

IPC: H02J7/00 ,  H02J7/04

Abstract: Provided are a battery charging method and an electronic device. The electronic device includes a connector that includes a first terminal to which a voltage is applied by an external charger and a second terminal for transmitting and receiving data, and a first charging circuit configured to charge a battery of the electronic device by using the voltage applied to the first terminal. The first charging circuit may include a communication circuit configured to transmit information related to the battery through the second terminal, a voltage converter configured to convert a voltage supplied to the battery and a first controller circuit configured to obtain first information regarding a voltage of the battery, control the communication circuit to transmit the first information to a charger connected with the connector, and control the voltage converter to charge the battery using a voltage adjusted based on the first information by the charger, if the adjusted voltage is applied to the first terminal.

公开(公告)号：US10084332B2

公开(公告)日：2018-09-25

申请号：US14952002

申请日：2015-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Hui Han ,  Chul-Woo Park ,  Kisun Lee

IPC: H02J7/00 ,  H02J7/35

CPC classification number: H02J7/007 ,  H02J7/0055 ,  H02J7/35

Abstract: A method of performing a charging function by using different types of energy sources and an electronic device thereof are provided. The electronic device includes different types of circuits configured to acquire different types of energy sources, and a processor configured to determine an energy source for charging among the different types of energy sources based on respective current values for the different types of energy sources, and control the determined energy source for charging so as to be used in battery charging of the electronic device or in a system operation of the electronic device.

公开(公告)号：US09824755B2

公开(公告)日：2017-11-21

申请号：US14465995

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Kwang-Il Park ,  Hak-Soo Yu

IPC: G06F12/10 ,  G11C14/00 ,  G11C29/00 ,  G11C11/40 ,  G11C29/44

CPC classification number: G11C14/0018 ,  G11C11/40 ,  G11C29/702 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

公开(公告)号：US09711205B2

公开(公告)日：2017-07-18

申请号：US14874568

申请日：2015-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Chul-Woo Park ,  Young-Soo Sohn

IPC: G11C11/406 ,  G06F12/02 ,  G11C11/00 ,  G11C29/28 ,  G11C29/04 ,  G11C29/44

CPC classification number: G11C11/40615 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/005 ,  G11C29/28 ,  G11C2029/0409 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

公开(公告)号：US09558805B2

公开(公告)日：2017-01-31

申请号：US14083033

申请日：2013-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Uk-Song Kang ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jong-Pil Son

IPC: G06F13/00 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40607 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4087

Abstract: A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.

Abstract translation: 存储器模块包括多个存储器件和缓冲器芯片。 缓冲芯片管理存储器件。 缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。 缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。

公开(公告)号：US09390778B2

公开(公告)日：2016-07-12

申请号：US14798164

申请日：2015-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-A Kim ,  Dae-Sun Kim ,  Dae-Jeong Kim ,  Sung-Min Ryu ,  Kwang-Il Park ,  Chul-Woo Park ,  Young-Soo Sohn ,  Jae-Youn Youn

IPC: G11C8/12 ,  G11C8/08 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4097

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract translation: 半导体存储器件包括存储单元阵列，子字线驱动器和功率选择开关。 存储单元阵列包括耦合到字线的存储单元行。 子字线驱动器耦合到字线。 功率选择开关耦合到子字线驱动器。 每个电源选择开关控制从字线激活的第一字线的去激活电压电平和与第一字线相邻的第二字线的截止电压电平，使得去激活电压电平和截止电压电平 具有接地电压，第一负电压和第二负电压中的至少一个。 接地电压，第一负电压和第二负电压彼此具有不同的电压电平。

公开(公告)号：US09318185B2

公开(公告)日：2016-04-19

申请号：US14517255

申请日：2014-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua Kim ,  Chul-Woo Park

IPC: G11C11/406 ,  G11C11/408 ,  G11C5/04

CPC classification number: G11C11/4082 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.

Abstract translation: 存储器模块可以包括m个存储器件。 每个m个存储器件可以被划分为n个区域，每个区域包括对应于行地址的多个行，其中m和n是等于或大于2的整数。一种地址检测器，包括在每个m个存储器件中，其中 对于每个地址检测器，地址检测器可以被配置为在预定时间段内对包括在每个m个存储器件的一个区域中的特定行地址的访问次数进行计数，并且被配置为当 计数访问次数达到参考值。 每个最大计数地址生成器可以被配置为对与其他最大计数地址生成器计数访问的行地址集合不同的一组行地址来计数访问次数。

公开(公告)号：US09147500B2

公开(公告)日：2015-09-29

申请号：US13945007

申请日：2013-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Jin Kim ,  Hyung-Rok Oh ,  Dong-Seok Kang ,  Dong-Hyun Sohn ,  Sang-Beom Kang ,  Chul-Woo Park ,  Yun-Sang Lee

IPC: G11C11/00 ,  G11C29/10 ,  G11C11/16 ,  G11C29/32 ,  G11C29/34 ,  G11C29/26

CPC classification number: G11C29/10 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/32 ,  G11C29/34 ,  G11C2029/2602

Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

Abstract translation: 半导体存储器件包括存储单元阵列，模式寄存器组和测试电路。 存储单元阵列包括多个字线，多个位线和多个自旋转移转矩磁阻随机存取存储器（STT-MRAM）单元，每个STT-MRAM单元设置在每个字线的交叉区域 和位线，并且STT-MRAM单元包括磁隧道结（MTJ）元件和单元晶体管。 单元晶体管的栅极耦合到字线，单元晶体管的第一电极通过MTJ元件耦合到位线，并且单元晶体管的第二电极耦合到源极线。 模式寄存器组被配置为设置测试模式，并且测试电路被配置为通过使用模式寄存器集执行测试操作。

公开(公告)号：US09064546B2

公开(公告)日：2015-06-23

申请号：US14069188

申请日：2013-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Young-Soo Sohn ,  Chul-Woo Park ,  Cheol-Heui Park

IPC: G11C8/10 ,  G11C8/06 ,  G11C7/12 ,  G11C29/18 ,  G11C16/24 ,  G11C29/12

CPC classification number: G11C8/06 ,  G11C7/12 ,  G11C8/10 ,  G11C16/24 ,  G11C29/18 ,  G11C2029/1204 ,  G11C2029/1806

Abstract: A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.

Abstract translation: 可以提供一种存储器件，其包括包括多个子阵列的存储单元阵列，每个子阵列具有连接到位线的多个存储器单元; 配置为接收行地址和列地址的地址缓冲器; 以及列解码器，被配置为从地址缓冲器接收列地址，并且对于每个子阵列，基于应用的不同偏移值从多个列选择线中选择与列地址对应的列选择线 分别到子阵列。 所选择的列选择线分别对应于具有不同物理位置的位线，根据不同的偏移值。