公开(公告)号：US11616070B2

公开(公告)日：2023-03-28

申请号：US17155225

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyoun Jo ,  Kohji Kanamori ,  Kwangyoung Jung ,  Jeehoon Han

IPC: H01L27/11519 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/522

Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

公开(公告)号：US11594544B2

公开(公告)日：2023-02-28

申请号：US16942456

申请日：2020-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Younghwan Son ,  Seogoo Kang ,  Jesuk Moon ,  Junghoon Jun ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565

Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.

公开(公告)号：US20220139831A1

公开(公告)日：2022-05-05

申请号：US17475128

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H01L27/11582 ,  H01L29/423

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US09553098B2

公开(公告)日：2017-01-24

申请号：US14858756

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Hyun You ,  Hyeong Park ,  Bongtae Park ,  Jeehoon Han

IPC: H01L27/115 ,  H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Abstract translation: 半导体器件包括设置在半导体衬底上的多条线，以及与线路延伸线上间隔开的剩余线图案。 这些线包括与其余线图案相邻的第一端部。 剩余的线图案包括与线相邻的第二端部。 第一端部和第二端部形成为相对于彼此具有镜像对称性。

公开(公告)号：US09171853B2

公开(公告)日：2015-10-27

申请号：US14200610

申请日：2014-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Hyun You ,  Hyeong Park ,  Bongtae Park ,  Jeehoon Han

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Abstract translation: 半导体器件包括设置在半导体衬底上的多条线，以及与线路延伸线上间隔开的剩余线图案。 这些线包括与其余线图案相邻的第一端部。 剩余的线图案包括与线相邻的第二端部。 第一端部和第二端部形成为相对于彼此具有镜像对称性。

公开(公告)号：US12279421B2

公开(公告)日：2025-04-15

申请号：US18190253

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyoun Jo ,  Kohji Kanamori ,  Kwangyoung Jung ,  Jeehoon Han

IPC: H10B41/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

公开(公告)号：US20250008737A1

公开(公告)日：2025-01-02

申请号：US18882427

申请日：2024-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun Chun ,  Shinhwan Kang ,  Jihwan Kim ,  Jeehoon Han

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device includes a lower structure including a peripheral circuit; a stack structure on the lower structure, extending from a memory cell array region to a stepped region, and including a gate stacked region, and an insulator stacked regions arranged in the stepped region in a first direction; a capping insulating structure on the stack structure; and separation structures passing through the gate stacked region. The stack structure includes interlayer insulating layers and horizontal layers, alternately and repeatedly stacked, the horizontal layers include gate horizontal layers and insulating horizontal layers, the gate stacked region includes the gate horizontal layers, each of the insulator stacked regions includes the insulating horizontal layers, in the stepped region, the stack structure includes a first stepped region, a connection stepped region, and a second stepped region.

公开(公告)号：US12183677B2

公开(公告)日：2024-12-31

申请号：US18526208

申请日：2023-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US12167598B2

公开(公告)日：2024-12-10

申请号：US17703130

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kanamori Kohji ,  Jeehoon Han

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/48 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.

公开(公告)号：US20240355735A1

公开(公告)日：2024-10-24

申请号：US18419856

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemi LEE ,  Seungyoon Kim ,  Heesuk Kim ,  Sangjae Lee ,  Jaehoon Lee ,  Juyoung Lim ,  Minkyu Chung ,  Sanghun Chun ,  Jeehoon Han

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a plate layer, gate electrodes and interlayer insulating layers alternately stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and forming a first stack structure and a second stack structure on the first stack structure, a channel structure penetrating through the gate electrodes and extending in the first direction, and a contact plug extending in the first direction and electrically connected to one of the gate electrodes, wherein the second stack structure includes a first gate electrode on a lowermost portion, a first interlayer insulating layer on the first gate electrode, and a second interlayer insulating layer on the first interlayer insulating layer, and the first interlayer insulating layer has a first thickness, and the second interlayer insulating layer has a second thickness smaller than the first thickness.