公开(公告)号：US10354955B2

公开(公告)日：2019-07-16

申请号：US15687362

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Bin Yang ,  Junjing Bao

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  C01B32/182 ,  H01L29/78 ,  H01L21/8234

Abstract: An integrated circuit may include multiple back-end-of-line (BEOL) interconnect layers. The BEOL interconnect layers may include conductive lines and conductive vias. The integrated circuit may further include an interlayer dielectric (ILD) between the BEOL interconnect layers. The ILD may include the conductive lines and the conductive vias. At least a portion of the ILD may include a low-K insulating graphene alloy.

公开(公告)号：US11855198B2

公开(公告)日：2023-12-26

申请号：US16844479

申请日：2020-04-09

Applicant: QUALCOMM Incorporated

Inventor： Chenjie Tang ,  Ye Lu ,  Peijie Feng ,  Junjing Bao

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42316 ,  H01L29/66462

Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

公开(公告)号：US11380685B2

公开(公告)日：2022-07-05

申请号：US17061941

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Ye Lu ,  Chenjie Tang ,  Peijie Feng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/092

Abstract: Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.

公开(公告)号：US11189617B2

公开(公告)日：2021-11-30

申请号：US16774278

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Ye Lu ,  Junjing Bao ,  Chenjie Tang

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10 ,  H01L27/092 ,  H01L29/49 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306

Abstract: Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.

公开(公告)号：US11004784B2

公开(公告)日：2021-05-11

申请号：US16158742

申请日：2018-10-12

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Ye Lu ,  Chao Song

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/58 ,  H01G4/06 ,  H01L49/02

Abstract: Certain aspects of the present disclosure provide a metal-on-metal (MoM) capacitor with metal layers, each layer having two different electrical conductors with orthogonally-arranged conductive arteries and orthogonally-oriented conductive fingers. One exemplary MoM capacitor generally includes a plurality of metal layers, wherein a first metal layer in the plurality of metal layers comprises a first electrical conductor providing a first node of the MoM capacitor and a second electrical conductor providing a second node of the MoM capacitor. According to aspects, the first electrical conductor comprises a first plurality of conductive fingers and the second electrical conductor comprises a second plurality of conductive fingers. Further, conductive fingers of the first plurality of conductive fingers are interdigitated with conductive fingers of the second plurality of conductive fingers. Additionally, the first electrical conductor in the first metal layer is oriented orthogonal to the second electrical conductor in the first metal layer.

公开(公告)号：US10972068B2

公开(公告)日：2021-04-06

申请号：US16023186

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Chao Song ,  Haitao Cheng ,  Ye Lu ,  Dongjiang Qiao

IPC: H03H7/30 ,  H03H1/02 ,  H03H3/00 ,  H03H7/06 ,  H01L49/02 ,  H01L23/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip.

公开(公告)号：US10964380B1

公开(公告)日：2021-03-30

申请号：US16784149

申请日：2020-02-06

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Yandong Gao ,  Xia Li ,  Ye Lu ,  Xiaochun Zhu ,  Xiaonan Chen

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/56 ,  G11C11/419 ,  H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

公开(公告)号：US10930730B2

公开(公告)日：2021-02-23

申请号：US15816295

申请日：2017-11-17

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Yun Yue ,  Phanikumar Konkapaka ,  Bin Yang ,  Chuan-Hsing Chen

IPC: H01L23/52 ,  H01L27/08 ,  H01L29/06 ,  H01L23/522 ,  H01L29/78 ,  H01L29/93

Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.

公开(公告)号：US10665370B2

公开(公告)日：2020-05-26

申请号：US16058928

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Chao Song ,  Ye Lu

IPC: H01C3/02 ,  H01L49/02 ,  H01L27/02 ,  H01C17/04 ,  H01C3/16 ,  G06F30/36 ,  G06F30/3312

Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.

公开(公告)号：US10651268B2

公开(公告)日：2020-05-12

申请号：US16009976

申请日：2018-06-15

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Ye Lu ,  Chao Song

IPC: H01L29/00 ,  H01L49/02

Abstract: A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.