公开(公告)号：US20200152739A1

公开(公告)日：2020-05-14

申请号：US16189855

申请日：2018-11-13

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Ye Lu

IPC: H01L29/08 ,  H01L29/24 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L21/768 ,  H01L21/02

Abstract: A transistor comprises a substrate, a first buffer layer on the substrate, a source region, a drain region, and a channel region on the first buffer layer, a gate on the channel region, a source contact, and a drain contact. The source contact is configured to contact at least three sides of the source region and the drain contact is configured to contact at least three sides of the drain region to lower contact resistance in the source region and in the drain region.

公开(公告)号：US10482929B2

公开(公告)日：2019-11-19

申请号：US15817441

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: G11C16/04 ,  G11C5/02 ,  G06N3/08 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/16 ,  G11C11/22 ,  G11C11/54 ,  G11C13/00

Abstract: Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

公开(公告)号：US10475889B1

公开(公告)日：2019-11-12

申请号：US15997991

申请日：2018-06-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Gengming Tao ,  Bin Yang

IPC: H01L29/20 ,  H01L29/66 ,  H03F3/21 ,  H01L29/08 ,  H01L29/78

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a semiconductor region disposed adjacent to the substrate, first fin(s) disposed adjacent to the semiconductor region, first gate region(s) disposed adjacent to the first fin(s), first drain contact(s) disposed above the first fin(s), first source contact(s) disposed below the substrate, a second fin disposed above the semiconductor region, and a second gate region, second source contact and second drain contact disposed adjacent to the second fin and above the semiconductor region. First path(s) are formed between the first drain contact(s) and the first source contact(s) for current flow(s) through the first fin(s) in a vertical direction along the first path(s). A second path is formed between the second source contact and the second drain contact for current flow through the second fin in a horizontal direction along the second path.

公开(公告)号：US10461164B2

公开(公告)日：2019-10-29

申请号：US15685877

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Periannan Chidambaram

IPC: H01L29/423 ,  H01L29/66

Abstract: A compound semiconductor field effect transistor (FET) may include gallium nitride (GaN) and alloy material layers. The compound semiconductor FET may also include a pair of L-shaped contacts on the GaN and alloy material layers. The compound semiconductor FET may also include a pair of gate spacers between the L-shaped contacts and on the GaN and alloy material layers, each of the pair of gate spacers contacting one of the L-shaped contacts. The compound semiconductor FET may further include a base gate between the pair of gate spacers and on the GaN and alloy material layers, in which the pair of L-shaped contacts are self-aligned with the base gate.

公开(公告)号：US10224368B2

公开(公告)日：2019-03-05

申请号：US15639099

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jimmy Jianan Kan ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: G11C11/00 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

公开(公告)号：US10186514B1

公开(公告)日：2019-01-22

申请号：US15696630

申请日：2017-09-06

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Xia Li ,  Bin Yang

IPC: H01L27/11 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/205 ,  H01L29/737 ,  H01L21/02 ,  H01L29/66 ,  H01L27/06 ,  G11C11/419 ,  H01L29/20 ,  H01L27/07

Abstract: Bi-stable static random access memory (SRAM) bit cells formed from III-V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate, first well layer formed over substrate from a III-V compound doped with a first type material, and second well layer formed over first well layer from a III-V compound doped with a second type material. Channel layer is formed over second well layer from a III-V compound doped with the first type material. Source and drain regions are formed over channel layer from a III-V compound doped with the first type material, and gate region is formed over channel layer. Bipolar junction transistors (BJTs) are formed such that a data value can be stored in second well layer. Collector tap electrode is configured to provide access to collector of each BJT for reading or writing data.

公开(公告)号：US20190006415A1

公开(公告)日：2019-01-03

申请号：US15639099

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jimmy Jianan Kan ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

公开(公告)号：US10170610B1

公开(公告)日：2019-01-01

申请号：US15922951

申请日：2018-03-16

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/66

Abstract: In certain aspects, a pseudomorphic high electron mobility transistor (pHEMT) comprises a substrate layer, a bottom barrier layer on the substrate layer, a channel layer on the bottom barrier layer, an upper barrier on the channel layer, and a source and a drain on the upper barrier layer. The source and the drain each has a cap layer, an Ohmic contact layer on the cap layer, and a metal contact layer on the Ohmic contact layer. The Ohmic contact layer has a smaller bandgap than the cap layer. The pHEMT further comprises a gate metal stack on the upper barrier layer.

公开(公告)号：US10062683B1

公开(公告)日：2018-08-28

申请号：US15587837

申请日：2017-05-05

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao

IPC: H01L29/15 ,  H01L27/06 ,  H01L49/02 ,  H01L29/778 ,  H01L29/737 ,  H01L29/20 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8252 ,  H01L21/768 ,  H01L23/66

Abstract: An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound semiconductor circuitry may also include a high-Q inductor device. The integrated compound semiconductor may further include a back-end-of-line interconnect layer electrically contacting the high-Q inductor device and the compound semiconductor transistor, the back-end-of-line interconnect layer comprising a gold base layer and a copper interconnect layer.

公开(公告)号：US11437781B2

公开(公告)日：2022-09-06

申请号：US16803668

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/343 ,  H01S5/042 ,  H01S5/34

Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.