公开(公告)号：US20150109843A1

公开(公告)日：2015-04-23

申请号：US14152248

申请日：2014-01-10

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G11C5/02 ,  H01L23/00 ,  H04L12/933

CPC classification number: G11C5/02 ,  G06F1/3225 ,  G06F1/3275 ,  G11C5/025 ,  G11C5/063 ,  H01L24/89 ,  H01L27/0688 ,  H01L2924/1434 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/13 ,  Y02D10/14

Abstract: Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use.

Abstract translation: 公开了具有垂直存储器组件的单片三维（3D）集成电路（IC）（3DIC）。 使用具有用于块间路由选择的紧密垂直单片中间层通道（MIV）的三维存储器交叉结构架构，用于块访问的每层级多路复用器，以缩短整体导体长度并降低电阻 - 电容（RC）延迟。 消除这种长的十字准线会降低交叉开关的RC延迟，并通常提高性能和速度。 此外，消除长的横向横梁使得导线布线更容易。 MIVs具有较小的长度，可以在不需要中继器的情况下工作（与长十字准线不同），并且可以使用控制逻辑来基于使用配置存储体。

公开(公告)号：US20140149958A1

公开(公告)日：2014-05-29

申请号：US13792384

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/66

Abstract: The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

Abstract translation: 所公开的实施例涉及用于使用提供对现有3D设计方法的显着改进的2D和3D块的混合来布局规划集成电路设计的系统和方法。 所公开的实施例提供了更好的平面图解决方案，其进一步最小化电线长度并提高设计的整体功率/性能包络。 所公开的方法可以用于构建新的3D IP块，以用于使用单片3D集成技术构建的设计中。

公开(公告)号：US11004780B2

公开(公告)日：2021-05-11

申请号：US16688057

申请日：2019-11-19

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Yang Du ,  Robert Philip Gilmore

IPC: H01L23/498 ,  H01L21/768 ,  G06F30/39

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

公开(公告)号：US10510651B2

公开(公告)日：2019-12-17

申请号：US16220764

申请日：2018-12-14

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Yang Du ,  Robert Philip Gilmore

IPC: H01L23/498 ,  H01L21/768 ,  G06F17/50

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

公开(公告)号：US20180286800A1

公开(公告)日：2018-10-04

申请号：US15472614

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US20180260360A1

公开(公告)日：2018-09-13

申请号：US15452299

申请日：2017-03-07

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Amin Ansari ,  Yang Du

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F15/80 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/384 ,  G06F9/3867 ,  G06F12/0875 ,  G06F15/76 ,  G06F15/803 ,  G06F2212/452 ,  H01L25/0657 ,  H01L27/0688

Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.

公开(公告)号：US09629233B2

公开(公告)日：2017-04-18

申请号：US14732787

申请日：2015-06-08

Applicant: QUALCOMM Incorporated

Inventor： Mehdi Saeidi ,  Arpit Mittal ,  Emil Rahim ,  Rajat Mittal ,  Kambiz Samadi

IPC: H05K7/20 ,  H05K1/02 ,  G05B15/02 ,  H01L23/473

CPC classification number: H05K1/0203 ,  G05B15/02 ,  H05K1/0209 ,  H05K1/0272 ,  H05K7/20145 ,  H05K7/20172 ,  H05K7/20209 ,  H05K2201/064

Abstract: Methods and apparatus for implementing a synthetic jet to cool a device are provided. Examples of the techniques keep a device case cool enough to be hand-held, while allowing a higher temperature of a circuit component located in the case, to maximize circuit performance. In an example, provided is a mobile device including a synthetic jet configured to transfer heat within the mobile device. The synthetic jet can be embedded in a circuit board inside the mobile device such that the circuit board defines at least a portion of a chamber of the synthetic jet and defines an orifice of the synthetic jet. The device case can define at least one fluid channel inside the mobile device. Also, the circuit board can define a synthetic jet outlet configured to direct a fluid at the at least one fluid channel. Also provided are methods for controlling a synthetic jet.

公开(公告)号：US09147438B2

公开(公告)日：2015-09-29

申请号：US14152248

申请日：2014-01-10

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G11C17/00 ,  G11C5/02 ,  H04L12/933 ,  H01L23/00 ,  G06F1/32 ,  H01L27/06

CPC classification number: G11C5/02 ,  G06F1/3225 ,  G06F1/3275 ,  G11C5/025 ,  G11C5/063 ,  H01L24/89 ,  H01L27/0688 ,  H01L2924/1434 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/13 ,  Y02D10/14

Abstract: Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use.

Abstract translation: 公开了具有垂直存储器组件的单片三维（3D）集成电路（IC）（3DIC）。 使用具有用于块间路由选择的紧密垂直单片中间层通道（MIV）的三维存储器交叉结构架构，用于块访问的每层级多路复用器，以缩短整体导体长度并降低电阻 - 电容（RC）延迟。 消除这种长的十字准线会降低交叉开关的RC延迟，并通常提高性能和速度。 此外，消除长的横向横梁使得导线布线更容易。 MIVs具有较小的长度，可以在不需要中继器的情况下工作（与长十字准线不同），并且可以使用控制逻辑来基于使用配置存储体。

公开(公告)号：US09123721B2

公开(公告)日：2015-09-01

申请号：US14132098

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L21/768 ,  H01L23/522 ,  G06F17/50

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US09098666B2

公开(公告)日：2015-08-04

申请号：US13792486

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Jing Xie ,  Yang Du

IPC: G06F17/50 ,  H01L23/522 ,  G11C5/14 ,  G06F1/32

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Abstract translation: 本发明的示例性实施例涉及用于设计用于集成电路的时钟分配网络的系统和方法。 这些实施例确定了时钟偏移的关键来源，紧密地控制时钟的定时并将该时序构建到整个时钟分配网络和集成电路设计中。 所公开的实施例将时钟分配网络（CDN），即时钟生成电路，布线，缓冲和寄存器与逻辑的其余部分分开，以改进时钟树设计并减少面积占用。 在一个实施例中，CDN被分离成3D集成电路的单独层，并且CDN通过高密度层间通孔连接到逻辑层。 这些实施例对于使用单片3D集成电路的实现特别有利。