公开(公告)号：US09530509B2

公开(公告)日：2016-12-27

申请号：US14727878

申请日：2015-06-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Chi-Heng Yang

IPC: G06F12/00 ,  G11C16/14 ,  G06F3/06 ,  G06F12/08 ,  G11C16/26 ,  G11C29/44

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/0409 ,  G11C2211/5648

Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.

Abstract translation: 提供数据编程方法，存储器存储装置和存储器控制电路单元。 该方法包括：接收第一数据并将第一数据编程到第一较低物理编程单元中; 接收第二数据; 响应于要被编程到与第一下部物理编程单元相对应的第一上部物理编程单元的第二数据，执行不包括通过使用默认读取电压读取第一下部物理编程单元的第一数据获取操作; 以及根据通过第一数据获取操作获得的第三数据将第二数据编程到第一上层物理编程单元中。

公开(公告)号：US09431132B2

公开(公告)日：2016-08-30

申请号：US14307509

申请日：2014-06-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Li-Chun Liang ,  Kuo-Hsin Lai ,  Pei-Yu Shih ,  Tien-Ching Wang

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  G11B20/18 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/106 ,  G06F11/1068 ,  G06F11/1076 ,  G11B20/1833 ,  G11C2029/0411

Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.

Abstract translation: 提供数据管理方法，以及存储器控制电路单元和使用该数据管理方法的存储器存储装置。 所述数据管理方法包括：根据第一读取命令从第一物理擦除单元读取第一数据流，其中所述第一数据流包括第一用户数据，第一纠错码和第一错误检测码。 该方法还包括：使用第一纠错码和错误检测码对第一用户数据进行解码，并确定第一用户数据是否被成功解码。 该方法还包括：如果第一用户数据被成功解码，则响应于第一读取命令，将通过将第一用户数据正确解码而获得的校正用户数据发送给主机系统。

公开(公告)号：US20160098316A1

公开(公告)日：2016-04-07

申请号：US14565437

申请日：2014-12-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Shao-Wei Yen ,  Tien-Ching Wang ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai ,  Li-Chun Liang

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.

Abstract translation: 提供了一种用于可重写非易失性存储器模块，存储器存储装置和存储器控制电路单元的错误处理方法。 可重写非易失性存储器模块包括多个存储单元。 该错误处理方法包括：从存储器单元发送用于读取多个位的第一读取命令序列; 对比特执行第一解码; 如果所述比特具有至少一个错误，则确定每个错误是否属于第一类型错误或第二类型错误; 如果所述第一错误属于所述第一类型错误，则记录所述至少一个错误中的第一错误的相关信息; 并且如果第一错误属于第二类型错误，则不记录第一错误的相关信息。 因此，可以适当地处理特定类型的错误。

公开(公告)号：US20150293811A1

公开(公告)日：2015-10-15

申请号：US14295355

申请日：2014-06-04

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US09019770B2

公开(公告)日：2015-04-28

申请号：US13901571

申请日：2013-05-24

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/04 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3436 ,  G11C16/349

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing.

Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括将测试电压施加到可重写非易失性存储器模块的字线以读取多个验证位数据。 该方法还包括计算在验证位数据中识别为第一状态的位数据的变化，获得基于该变化设置的新的读取电压值，并且用新的读取电压值集更新用于字线的阈值电压 。 该方法还包括使用更新的阈值电压来从连接到字线的存储器单元形成的物理页读取数据。 因此，可以正确地识别可重写非易失性存储器模块中的存储单元的存储状态，从而防止存储在存储单元中的数据丢失。