公开(公告)号：US11580621B2

公开(公告)日：2023-02-14

申请号：US17113397

申请日：2020-12-07

Applicant: MEDIATEK INC.

Inventor： Jen Cheng Lung ,  Pei-Kuei Tsung ,  Chih-Wei Chen ,  Yao-Sheng Wang ,  Shih-Che Chen ,  Yu-Sheng Lin ,  Chih-Wen Goo ,  Shih-Chin Lin ,  Huang Tsung-Shian ,  Ying-Chieh Chen

IPC: G06T5/00 ,  G06T3/00 ,  G06T7/254 ,  G06T3/40 ,  G06T5/50

Abstract: Aspects of the disclosure provide a device for processing frames with aliasing artifacts. For example, the device can include a motion estimation circuit, a warping circuit coupled to the motion estimation circuit, and a temporal decision circuit coupled to the warping circuit. The motion estimation circuit can estimate a motion value between a current frame and a previous frame. The warping circuit can warp the previous frame based on the motion value such that the warped previous frame is aligned with the current frame and determine whether the current frame and the warped previous frame are consistent. The temporal decision circuit can generate an output frame, the output frame including either the current frame and the warped previous frame when the current frame and the warped previous frame are consistent, or the current frame when the current frame and the warped previous frame are not consistent.

公开(公告)号：US20220199593A1

公开(公告)日：2022-06-23

申请号：US17492693

申请日：2021-10-04

Applicant: MEDIATEK INC.

Inventor： Bo-Jiun Yang ,  Wen-Sung Hsu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Kun-Ting Hung

IPC: H01L25/10 ,  H01L25/065

Abstract: A semiconductor device includes a bottom package, a top package stacked on the bottom package, and an interposer disposed between the bottom package and the top package. The top package is electrically connected to the interposer through a plurality of peripheral solder balls. At least a dummy thermal feature is disposed on the interposer and surrounded by the plurality of peripheral solder balls.

公开(公告)号：US20220115303A1

公开(公告)日：2022-04-14

申请号：US17460352

申请日：2021-08-30

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang ,  Yin-Fa Chen ,  Shih-Chin Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.

公开(公告)号：US09881902B2

公开(公告)日：2018-01-30

申请号：US15162724

申请日：2016-05-24

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng

IPC: H01L25/16 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L21/52

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/52 ,  H01L21/568 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

公开(公告)号：US20170084541A1

公开(公告)日：2017-03-23

申请号：US15162760

申请日：2016-05-24

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.

公开(公告)号：US20160263709A1

公开(公告)日：2016-09-15

申请号：US14918698

申请日：2015-10-21

Applicant: MEDIATEK Inc.

Inventor： Tao Cheng ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: B23K35/02 ,  B23K35/26 ,  B23K35/30 ,  H01L23/00

CPC classification number: B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  B23K35/264 ,  B23K35/30 ,  B23K2101/40 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

Abstract translation: 半导体封装包括第一基板，第二基板，复合焊球和第一半导体部件。 复合焊球包括芯，封装层和阻挡层。 复合焊球设置在第一基板和第二基板之间，用于电连接第一基板和第二基板。 阻挡层设置在芯和封装层之间。 其中阻挡层的熔点高于芯的熔点，芯的熔点高于封装层的熔点。 第一半导体部件设置在第一基板和第二基板之间。

公开(公告)号：US11983848B2

公开(公告)日：2024-05-14

申请号：US18151104

申请日：2023-01-06

Applicant: MEDIATEK INC.

Inventor： Cheng-Lung Jen ,  Pei-Kuei Tsung ,  Chih-Wei Chen ,  Yao-Sheng Wang ,  Shih-Che Chen ,  Yu-Sheng Lin ,  Chih-Wen Goo ,  Shih-Chin Lin ,  Tsung-Shian Huang ,  Ying-Chieh Chen

IPC: G06T5/00 ,  G06T3/00 ,  G06T3/40 ,  G06T3/4053 ,  G06T5/50 ,  G06T7/254

CPC classification number: G06T5/002 ,  G06T3/0093 ,  G06T3/4053 ,  G06T5/50 ,  G06T7/254 ,  G06T2207/20084 ,  G06T2207/20224

Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.

公开(公告)号：US11869831B2

公开(公告)日：2024-01-09

申请号：US17460352

申请日：2021-08-30

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang ,  Yin-Fa Chen ,  Shih-Chin Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/48 ,  H01L2224/48175

Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.

公开(公告)号：US20230307421A1

公开(公告)日：2023-09-28

申请号：US18203631

申请日：2023-05-30

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Tai-Yu Chen ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L24/17 ,  H10B80/00

Abstract: A package-on-package includes a first package and a second package on the first package. The first package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and an IC device are mounted on the bottom substrate in a side-by-side configuration. The logic die has a thickness not less than 125 micrometer. Copper cored solder balls are disposed between around the logic die and the IC device to electrically connect the bottom substrate with the top substrate. A sealing resin is filled into the gap between the bottom substrate and the top substrate and seals the logic die, the IC device, and the copper cored solder balls in the gap.

公开(公告)号：US20230282604A1

公开(公告)日：2023-09-07

申请号：US18106499

申请日：2023-02-07

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Isabella Song ,  Wen-Chin Tsai

IPC: H01L23/00 ,  H01L25/16 ,  H10B80/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/32 ,  H01L24/73 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L24/16 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/3135 ,  H01L23/291 ,  H01L23/293 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/14361 ,  H01L2924/1431 ,  H01L2224/13644 ,  H01L2224/13082 ,  H01L2224/13575 ,  H01L2224/13005 ,  H01L2224/1357 ,  H01L2924/1011

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate in a flip-chip fashion. The logic die has a thickness of 125-350 micrometers. The logic die comprises an active front side, a passive rear side, and an input/output pad provided on the active front side. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap.