公开(公告)号：US11580621B2

公开(公告)日：2023-02-14

申请号：US17113397

申请日：2020-12-07

Applicant: MEDIATEK INC.

Inventor： Jen Cheng Lung ,  Pei-Kuei Tsung ,  Chih-Wei Chen ,  Yao-Sheng Wang ,  Shih-Che Chen ,  Yu-Sheng Lin ,  Chih-Wen Goo ,  Shih-Chin Lin ,  Huang Tsung-Shian ,  Ying-Chieh Chen

IPC: G06T5/00 ,  G06T3/00 ,  G06T7/254 ,  G06T3/40 ,  G06T5/50

Abstract: Aspects of the disclosure provide a device for processing frames with aliasing artifacts. For example, the device can include a motion estimation circuit, a warping circuit coupled to the motion estimation circuit, and a temporal decision circuit coupled to the warping circuit. The motion estimation circuit can estimate a motion value between a current frame and a previous frame. The warping circuit can warp the previous frame based on the motion value such that the warped previous frame is aligned with the current frame and determine whether the current frame and the warped previous frame are consistent. The temporal decision circuit can generate an output frame, the output frame including either the current frame and the warped previous frame when the current frame and the warped previous frame are consistent, or the current frame when the current frame and the warped previous frame are not consistent.

公开(公告)号：US20230328202A1

公开(公告)日：2023-10-12

申请号：US18128180

申请日：2023-03-29

Applicant: MEDIATEK INC.

Inventor： Yao-Sheng Wang ,  Pei-Kuei Tsung ,  Chia-Ni Lu ,  Yu-Sheng Lin ,  Chien-Yu Huang ,  Chih-Wen Goo ,  Cheng-Lung Jen

IPC: H04N7/01

CPC classification number: H04N7/014 ,  H04N7/0127

Abstract: A frame interpolation method for generating a third image frame interpolated between a first image frame and a second image frame includes: performing motion estimation upon a first input image frame and a second input image frame, to obtain a single-directional motion, wherein the first input image frame is derived from the first image frame, and the second input image frame is derived from the second image frame; scaling the single-directional motion according to a time point of the third image frame, to generate a scaled motion; deriving a forward-warped result from a result of performing a forward warping operation and a first inverse operation upon the scaled motion; performing a second inverse operation upon the forward-warped result, to generate an inversed result; and generating the third image frame according to the first image frame, the second image frame, the forward-warped result, and the inversed result.

公开(公告)号：US20210287338A1

公开(公告)日：2021-09-16

申请号：US17118162

申请日：2020-12-10

Applicant: MediaTek Inc.

Inventor： Ming-En Shih ,  Ping-Yuan Tsai ,  Yu-Cheng Tseng ,  Kuo-Chen Huang ,  Kuo-Chiang Lo ,  Hsin-Min Peng ,  Chun Hsien Wu ,  Pei-Kuei Tsung ,  Tung-Chien Chen ,  Yao-Sheng Wang ,  Cheng Lung Jen ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Sheng Lin ,  Tsu Jui Hsu

IPC: G06T3/40 ,  G06T7/00 ,  G06T5/00 ,  G06N3/04 ,  G06N3/08

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligent (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

公开(公告)号：US12062151B2

公开(公告)日：2024-08-13

申请号：US17118162

申请日：2020-12-10

Applicant: MediaTek Inc.

Inventor： Ming-En Shih ,  Ping-Yuan Tsai ,  Yu-Cheng Tseng ,  Kuo-Chen Huang ,  Kuo-Chiang Lo ,  Hsin-Min Peng ,  Chun Hsien Wu ,  Pei-Kuei Tsung ,  Tung-Chien Chen ,  Yao-Sheng Wang ,  Cheng Lung Jen ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Sheng Lin ,  Tsu Jui Hsu

IPC: G06T3/4053 ,  G06F13/00 ,  G06N3/04 ,  G06N3/08 ,  G06T3/4046 ,  G06T5/70 ,  G06T7/00 ,  G09G5/391 ,  H01L21/033 ,  H04N9/31

CPC classification number: G06T3/4053 ,  G06F13/00 ,  G06N3/04 ,  G06N3/08 ,  G06T3/4046 ,  G06T5/70 ,  G06T7/0002 ,  G09G5/391 ,  H01L21/0338 ,  H04N9/3188 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30168

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

公开(公告)号：US20210287340A1

公开(公告)日：2021-09-16

申请号：US17167356

申请日：2021-02-04

Applicant: MediaTek Inc.

Inventor： Cheng Lung Jen ,  Pei-Kuei Tsung ,  Yao-Sheng Wang ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Cheng Tseng ,  Ming-En Shih ,  Kuo-Chiang Lo

IPC: G06T3/40 ,  G06N3/04 ,  G06K9/62 ,  H04L29/06

Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.

公开(公告)号：US20200327864A1

公开(公告)日：2020-10-15

申请号：US16819153

申请日：2020-03-15

Applicant: MEDIATEK INC.

Inventor： Cheng-Lung Jen ,  Pei-Kuei Tsung ,  Chih-Wen Goo ,  Yu-Cheng Tseng ,  Yu-Lin Hou ,  Kuo-Chiang Lo ,  Chia-Da Lee ,  Tung-Chien Chen

IPC: G09G5/00 ,  H04N9/64 ,  G09G5/10 ,  G09G5/02

Abstract: A video processing system includes an input port and a video processing circuit. The input port obtains device information of a display panel. The video processing circuit obtains an input frame and the device information, configures an image enhancement operation according to the device information, generates an output frame by performing the image enhancement operation upon the input frame, and transmits the output frame to the display panel for video playback.

公开(公告)号：US12010456B2

公开(公告)日：2024-06-11

申请号：US18128180

申请日：2023-03-29

Applicant: MEDIATEK INC.

Inventor： Yao-Sheng Wang ,  Pei-Kuei Tsung ,  Chia-Ni Lu ,  Yu-Sheng Lin ,  Chien-Yu Huang ,  Chih-Wen Goo ,  Cheng-Lung Jen

IPC: H04N7/01

CPC classification number: H04N7/014 ,  H04N7/0127

Abstract: A frame interpolation method for generating a third image frame interpolated between a first image frame and a second image frame includes: performing motion estimation upon a first input image frame and a second input image frame, to obtain a single-directional motion, wherein the first input image frame is derived from the first image frame, and the second input image frame is derived from the second image frame; scaling the single-directional motion according to a time point of the third image frame, to generate a scaled motion; deriving a forward-warped result from a result of performing a forward warping operation and a first inverse operation upon the scaled motion; performing a second inverse operation upon the forward-warped result, to generate an inversed result; and generating the third image frame according to the first image frame, the second image frame, the forward-warped result, and the inversed result.

公开(公告)号：US11983848B2

公开(公告)日：2024-05-14

申请号：US18151104

申请日：2023-01-06

Applicant: MEDIATEK INC.

Inventor： Cheng-Lung Jen ,  Pei-Kuei Tsung ,  Chih-Wei Chen ,  Yao-Sheng Wang ,  Shih-Che Chen ,  Yu-Sheng Lin ,  Chih-Wen Goo ,  Shih-Chin Lin ,  Tsung-Shian Huang ,  Ying-Chieh Chen

IPC: G06T5/00 ,  G06T3/00 ,  G06T3/40 ,  G06T3/4053 ,  G06T5/50 ,  G06T7/254

CPC classification number: G06T5/002 ,  G06T3/0093 ,  G06T3/4053 ,  G06T5/50 ,  G06T7/254 ,  G06T2207/20084 ,  G06T2207/20224

Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.

公开(公告)号：US20230401420A1

公开(公告)日：2023-12-14

申请号：US17838240

申请日：2022-06-12

Applicant: MediaTek Inc.

Inventor： Chih-Wen Goo ,  Pei-Kuei Tsung ,  Chih-Wei Chen ,  Mingen Shih ,  Shu-Hsin Chang ,  Po-Hua Huang ,  Ping-Yuan Tsai ,  Shih-Wei Hsieh ,  You Yu Nian

IPC: G06N3/04 ,  G06F9/30

CPC classification number: G06N3/04 ,  G06F9/3001

Abstract: A system receives a neural network model that includes asymmetric operations. Each asymmetric operation includes one or more fixed-point operands that are asymmetrically-quantized from corresponding floating-point operands. The system compiles a given asymmetric operation of the neural network model into a symmetric operation that includes a combined bias value. A compiler computes the combined bias value is a constant by merging at least zero points of input and output of the given asymmetric operation. The system then generates a symmetric neural network model including the symmetric operation for inference hardware to execute in fixed-point arithmetic.

公开(公告)号：US11836893B2

公开(公告)日：2023-12-05

申请号：US17167356

申请日：2021-02-04

Applicant: MediaTek Inc.

Inventor： Cheng Lung Jen ,  Pei-Kuei Tsung ,  Yao-Sheng Wang ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Cheng Tseng ,  Ming-En Shih ,  Kuo-Chiang Lo

IPC: G06T3/40 ,  G06N3/04 ,  H04L65/75 ,  G06F18/214 ,  G06V10/764 ,  G06V10/774 ,  G06V20/40

CPC classification number: G06T3/4053 ,  G06F18/214 ,  G06N3/04 ,  G06T3/4046 ,  G06T3/4076 ,  G06V10/764 ,  G06V10/774 ,  G06V20/41 ,  H04L65/75

Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.