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公开(公告)号：US12010456B2
公开(公告)日：2024-06-11
申请号：US18128180
申请日：2023-03-29
Applicant: MEDIATEK INC.
Inventor： Yao-Sheng Wang , Pei-Kuei Tsung , Chia-Ni Lu , Yu-Sheng Lin , Chien-Yu Huang , Chih-Wen Goo , Cheng-Lung Jen
IPC: H04N7/01
CPC classification number: H04N7/014 , H04N7/0127
Abstract: A frame interpolation method for generating a third image frame interpolated between a first image frame and a second image frame includes: performing motion estimation upon a first input image frame and a second input image frame, to obtain a single-directional motion, wherein the first input image frame is derived from the first image frame, and the second input image frame is derived from the second image frame; scaling the single-directional motion according to a time point of the third image frame, to generate a scaled motion; deriving a forward-warped result from a result of performing a forward warping operation and a first inverse operation upon the scaled motion; performing a second inverse operation upon the forward-warped result, to generate an inversed result; and generating the third image frame according to the first image frame, the second image frame, the forward-warped result, and the inversed result.
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公开(公告)号：US11983848B2
公开(公告)日：2024-05-14
申请号：US18151104
申请日：2023-01-06
Applicant: MEDIATEK INC.
Inventor： Cheng-Lung Jen , Pei-Kuei Tsung , Chih-Wei Chen , Yao-Sheng Wang , Shih-Che Chen , Yu-Sheng Lin , Chih-Wen Goo , Shih-Chin Lin , Tsung-Shian Huang , Ying-Chieh Chen
CPC classification number: G06T5/002 , G06T3/0093 , G06T3/4053 , G06T5/50 , G06T7/254 , G06T2207/20084 , G06T2207/20224
Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
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公开(公告)号：US11836893B2
公开(公告)日：2023-12-05
申请号：US17167356
申请日：2021-02-04
Applicant: MediaTek Inc.
Inventor： Cheng Lung Jen , Pei-Kuei Tsung , Yao-Sheng Wang , Chih-Wei Chen , Chih-Wen Goo , Yu-Cheng Tseng , Ming-En Shih , Kuo-Chiang Lo
IPC: G06T3/40 , G06N3/04 , H04L65/75 , G06F18/214 , G06V10/764 , G06V10/774 , G06V20/40
CPC classification number: G06T3/4053 , G06F18/214 , G06N3/04 , G06T3/4046 , G06T3/4076 , G06V10/764 , G06V10/774 , G06V20/41 , H04L65/75
Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.
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公开(公告)号：US12062151B2
公开(公告)日：2024-08-13
申请号：US17118162
申请日：2020-12-10
Applicant: MediaTek Inc.
Inventor： Ming-En Shih , Ping-Yuan Tsai , Yu-Cheng Tseng , Kuo-Chen Huang , Kuo-Chiang Lo , Hsin-Min Peng , Chun Hsien Wu , Pei-Kuei Tsung , Tung-Chien Chen , Yao-Sheng Wang , Cheng Lung Jen , Chih-Wei Chen , Chih-Wen Goo , Yu-Sheng Lin , Tsu Jui Hsu
IPC: G06T3/4053 , G06F13/00 , G06N3/04 , G06N3/08 , G06T3/4046 , G06T5/70 , G06T7/00 , G09G5/391 , H01L21/033 , H04N9/31
CPC classification number: G06T3/4053 , G06F13/00 , G06N3/04 , G06N3/08 , G06T3/4046 , G06T5/70 , G06T7/0002 , G09G5/391 , H01L21/0338 , H04N9/3188 , G06T2207/20081 , G06T2207/20084 , G06T2207/30168
Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.
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公开(公告)号：US20230334619A1
公开(公告)日：2023-10-19
申请号：US17722711
申请日：2022-04-18
Applicant: MediaTek Inc.
Inventor： Chih-Wei Chen , Pei-Kuei Tsung , Yao-Sheng Wang , Chun Chen Lin , Chia-Ching Lin , Hsiao-Chien Chiu
CPC classification number: G06T3/40 , G06T7/194 , H04N5/23296 , G06T7/571
Abstract: A device produces a dolly zoom effect with automatic focal length adjustment. The device uses a camera to capture an initial image including at least a foreground object and a background. The device includes a size tracking circuit to identify the size of the foreground object in the initial image. The device further includes a focal length control circuit. The focal length control circuit calculates an adjusted focal length of the camera to maintain the size of the foreground object in subsequently captured images.
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Patent Agency Ranking
公开(公告)号：US20230087097A1
公开(公告)日：2023-03-23
申请号：US17939939
申请日：2022-09-07
Applicant: MediaTek Inc.
Inventor： Yao-Sheng Wang , Pei-Kuei Tsung , Chiani Lu , Chao-Min Chang , Yu-Sheng Lin , Wai Mun Wong
Abstract: A booster engine enhances the quality of a frame sequence. The booster engine receives, from a first stage circuit, the frame sequence with quality degradation in at least a frame. The the quality degradation includes at least one of uneven resolution and uneven frame per second (FPS). The booster engine queries an information repository for reference information on the frame, using a query input based on at least a region of the frame to obtain a query output. The booster engine then applies a neural network to the query input and the query output to generate an optimized frame, and sends an enhanced frame sequence including the optimized frame to a second stage circuit.
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公开(公告)号：US20210334586A1
公开(公告)日：2021-10-28
申请号：US17191296
申请日：2021-03-03
Applicant: MediaTek Inc.
Inventor： Chih-Wei Chen , Pei-Kuei Tsung , Chia-Da Lee , Yao-Sheng Wang , Hsiao-Chien Chiu , Cheng Lung Jen , Yu-Cheng Tseng , Kuo-Chiang Lo , Yu Chieh Lan
IPC: G06K9/62 , G06T5/00 , G06F3/0482 , G06F3/0484 , G06F16/58 , G06F16/51 , G06N20/00
Abstract: An image processing circuit stores a training database and models in memory. The image processing circuit includes an attribute identification engine to identify an attribute from an input image according to a model stored in the memory. By enhancing the input image based on the identified attribute, a picture quality (PQ) engine in the image processing circuit generates an output image for display. The image processing circuit further includes a data collection module to generate a labeled image based on the input image labeled with the identified attribute, and to add the labeled image to the training database. A training engine in the image processing circuit then re-trains the model using the training database.
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公开(公告)号：US20210287340A1
公开(公告)日：2021-09-16
申请号：US17167356
申请日：2021-02-04
Applicant: MediaTek Inc.
Inventor： Cheng Lung Jen , Pei-Kuei Tsung , Yao-Sheng Wang , Chih-Wei Chen , Chih-Wen Goo , Yu-Cheng Tseng , Ming-En Shih , Kuo-Chiang Lo
Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.
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公开(公告)号：US12205237B2
公开(公告)日：2025-01-21
申请号：US17722711
申请日：2022-04-18
Applicant: MediaTek Inc.
Inventor： Chih-Wei Chen , Pei-Kuei Tsung , Yao-Sheng Wang , Chun Chen Lin , Chia-Ching Lin , Hsiao-Chien Chiu
Abstract: A device produces a dolly zoom effect with automatic focal length adjustment. The device uses a camera to capture an initial image including at least a foreground object and a background. The device includes a size tracking circuit to identify the size of the foreground object in the initial image. The device further includes a focal length control circuit. The focal length control circuit calculates an adjusted focal length of the camera to maintain the size of the foreground object in subsequently captured images.
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10.发明公开公开(公告)号：US20230328202A1
公开(公告)日：2023-10-12
申请号：US18128180
申请日：2023-03-29
Applicant: MEDIATEK INC.
Inventor： Yao-Sheng Wang , Pei-Kuei Tsung , Chia-Ni Lu , Yu-Sheng Lin , Chien-Yu Huang , Chih-Wen Goo , Cheng-Lung Jen
IPC: H04N7/01
CPC classification number: H04N7/014 , H04N7/0127
Abstract: A frame interpolation method for generating a third image frame interpolated between a first image frame and a second image frame includes: performing motion estimation upon a first input image frame and a second input image frame, to obtain a single-directional motion, wherein the first input image frame is derived from the first image frame, and the second input image frame is derived from the second image frame; scaling the single-directional motion according to a time point of the third image frame, to generate a scaled motion; deriving a forward-warped result from a result of performing a forward warping operation and a first inverse operation upon the scaled motion; performing a second inverse operation upon the forward-warped result, to generate an inversed result; and generating the third image frame according to the first image frame, the second image frame, the forward-warped result, and the inversed result.
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