公开(公告)号：US11836893B2

公开(公告)日：2023-12-05

申请号：US17167356

申请日：2021-02-04

Applicant: MediaTek Inc.

Inventor： Cheng Lung Jen ,  Pei-Kuei Tsung ,  Yao-Sheng Wang ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Cheng Tseng ,  Ming-En Shih ,  Kuo-Chiang Lo

IPC: G06T3/40 ,  G06N3/04 ,  H04L65/75 ,  G06F18/214 ,  G06V10/764 ,  G06V10/774 ,  G06V20/40

CPC classification number: G06T3/4053 ,  G06F18/214 ,  G06N3/04 ,  G06T3/4046 ,  G06T3/4076 ,  G06V10/764 ,  G06V10/774 ,  G06V20/41 ,  H04L65/75

Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.

公开(公告)号：US20210287338A1

公开(公告)日：2021-09-16

申请号：US17118162

申请日：2020-12-10

Applicant: MediaTek Inc.

Inventor： Ming-En Shih ,  Ping-Yuan Tsai ,  Yu-Cheng Tseng ,  Kuo-Chen Huang ,  Kuo-Chiang Lo ,  Hsin-Min Peng ,  Chun Hsien Wu ,  Pei-Kuei Tsung ,  Tung-Chien Chen ,  Yao-Sheng Wang ,  Cheng Lung Jen ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Sheng Lin ,  Tsu Jui Hsu

IPC: G06T3/40 ,  G06T7/00 ,  G06T5/00 ,  G06N3/04 ,  G06N3/08

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligent (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

公开(公告)号：US12062151B2

公开(公告)日：2024-08-13

申请号：US17118162

申请日：2020-12-10

Applicant: MediaTek Inc.

Inventor： Ming-En Shih ,  Ping-Yuan Tsai ,  Yu-Cheng Tseng ,  Kuo-Chen Huang ,  Kuo-Chiang Lo ,  Hsin-Min Peng ,  Chun Hsien Wu ,  Pei-Kuei Tsung ,  Tung-Chien Chen ,  Yao-Sheng Wang ,  Cheng Lung Jen ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Sheng Lin ,  Tsu Jui Hsu

IPC: G06T3/4053 ,  G06F13/00 ,  G06N3/04 ,  G06N3/08 ,  G06T3/4046 ,  G06T5/70 ,  G06T7/00 ,  G09G5/391 ,  H01L21/033 ,  H04N9/31

CPC classification number: G06T3/4053 ,  G06F13/00 ,  G06N3/04 ,  G06N3/08 ,  G06T3/4046 ,  G06T5/70 ,  G06T7/0002 ,  G09G5/391 ,  H01L21/0338 ,  H04N9/3188 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30168

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

公开(公告)号：US20210334586A1

公开(公告)日：2021-10-28

申请号：US17191296

申请日：2021-03-03

Applicant: MediaTek Inc.

Inventor： Chih-Wei Chen ,  Pei-Kuei Tsung ,  Chia-Da Lee ,  Yao-Sheng Wang ,  Hsiao-Chien Chiu ,  Cheng Lung Jen ,  Yu-Cheng Tseng ,  Kuo-Chiang Lo ,  Yu Chieh Lan

IPC: G06K9/62 ,  G06T5/00 ,  G06F3/0482 ,  G06F3/0484 ,  G06F16/58 ,  G06F16/51 ,  G06N20/00

Abstract: An image processing circuit stores a training database and models in memory. The image processing circuit includes an attribute identification engine to identify an attribute from an input image according to a model stored in the memory. By enhancing the input image based on the identified attribute, a picture quality (PQ) engine in the image processing circuit generates an output image for display. The image processing circuit further includes a data collection module to generate a labeled image based on the input image labeled with the identified attribute, and to add the labeled image to the training database. A training engine in the image processing circuit then re-trains the model using the training database.

公开(公告)号：US20210287340A1

公开(公告)日：2021-09-16

申请号：US17167356

申请日：2021-02-04

Applicant: MediaTek Inc.

Inventor： Cheng Lung Jen ,  Pei-Kuei Tsung ,  Yao-Sheng Wang ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Cheng Tseng ,  Ming-En Shih ,  Kuo-Chiang Lo

IPC: G06T3/40 ,  G06N3/04 ,  G06K9/62 ,  H04L29/06

Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.