公开(公告)号：US10553526B2

公开(公告)日：2020-02-04

申请号：US15460583

申请日：2017-03-16

Applicant: MEDIATEK, INC.

Inventor： Wen-Sung Hsu ,  Tzu-Hung Lin ,  Ta-Jen Yu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate having a die attach surface. A conductive trace is disposed on the substrate, wherein the conductive trace is elongated and carries a signal or a ground across at least a portion of the substrate. A die is mounted on the die attach surface of the substrate via a conductive pillar bump, the conductive pillar bump being rounded and elongated such that the conductive pillar bump extends along a length of the conductive trace and contacts the conductive trace at an end or at an intermediate portion thereof. The die further includes a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, and wherein the first edge is not adjacent to the second edge.

公开(公告)号：US10312210B2

公开(公告)日：2019-06-04

申请号：US15949868

申请日：2018-04-10

Applicant: MediaTek Inc.

Inventor： Ching-Liou Huang ,  Ta-Jen Yu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31

Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.

公开(公告)号：US10236242B2

公开(公告)日：2019-03-19

申请号：US15817780

申请日：2017-11-20

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ta-Jen Yu

IPC: H01L23/04 ,  H01L21/44 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H05K1/18 ,  H05K3/20

Abstract: A package substrate is provided. The package substrate includes a dielectric layer and a passive component embedded in the dielectric layer and contacting the dielectric layer. A circuit layer is embedded in the dielectric layer and has a first surface aligned with a second surface of the dielectric layer. A conductive structure is embedded in the dielectric layer and electrically connected to the passive component and the circuit layer. A chip package is also provided.

公开(公告)号：US10074581B2

公开(公告)日：2018-09-11

申请号：US15225927

申请日：2016-08-02

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.

公开(公告)号：US20180233476A1

公开(公告)日：2018-08-16

申请号：US15949868

申请日：2018-04-10

Applicant: MediaTek Inc.

Inventor： Ching-Liou Huang ,  Ta-Jen Yu

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/683

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16235 ,  H01L2224/17104 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.

公开(公告)号：US20230422525A1

公开(公告)日：2023-12-28

申请号：US18203666

申请日：2023-05-31

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H10B12/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H10B12/00 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.

公开(公告)号：US20230282625A1

公开(公告)日：2023-09-07

申请号：US18107520

申请日：2023-02-09

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Shih-Chin Lin ,  Tai-Yu Chen ,  Bo-Jiun Yang ,  Bing-Yeh Lin ,  Yung-Cheng Huang ,  Wen-Sung Hsu ,  Bo-Hao Ma ,  Isabella Song

IPC: H01L25/10 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/481 ,  H01L23/49866 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/48 ,  H01L2224/73204 ,  H01L2224/08112 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/183

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.

公开(公告)号：US20220392839A1

公开(公告)日：2022-12-08

申请号：US17886704

申请日：2022-08-12

Applicant: MediaTek Inc.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US20200152479A1

公开(公告)日：2020-05-14

申请号：US16743866

申请日：2020-01-15

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ta-Jen Yu

IPC: H01L21/48 ,  H01F17/00 ,  H05K3/30 ,  H05K3/18 ,  H05K3/10 ,  H05K3/00 ,  H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L23/66 ,  H01L23/64 ,  H01L23/538

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.

公开(公告)号：US10573615B2

公开(公告)日：2020-02-25

申请号：US14173976

申请日：2014-02-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.