公开(公告)号：US10522661B2

公开(公告)日：2019-12-31

申请号：US15926151

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li ,  Xin Miao

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/786 ,  H01L27/12

Abstract: Methods of forming a semiconductor device include forming stress liners in contact with both ends of a fin of alternating channel material and sacrificial material layers. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack on the suspended layers of channel material.

公开(公告)号：US10229857B2

公开(公告)日：2019-03-12

申请号：US15846968

申请日：2017-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jeehwan Kim ,  Juntao Li ,  Devendra K. Sadana

IPC: H01L21/8238 ,  H01L21/36 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L29/167 ,  H01L21/326 ,  H01L21/265 ,  H01L21/762

Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

公开(公告)号：US20180204921A1

公开(公告)日：2018-07-19

申请号：US15921877

申请日：2018-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/417 ,  H01L21/306 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L29/06 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L29/41783 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76243 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7834

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel.

公开(公告)号：US09997618B2

公开(公告)日：2018-06-12

申请号：US15476164

申请日：2017-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/6681 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7853

Abstract: Transistors and methods of forming the same include forming a fin of alternating layers of a channel material and a sacrificial material. Stress liners are formed in contact with both ends of the fin. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack is formed over and around the suspended layers of channel material.

公开(公告)号：US09966253B2

公开(公告)日：2018-05-08

申请号：US15054005

申请日：2016-02-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L29/06 ,  H01L21/02 ,  H01J9/02 ,  G01Q70/14 ,  G01Q70/16

CPC classification number: H01L21/02236 ,  G01Q70/14 ,  G01Q70/16 ,  H01J1/3044 ,  H01J9/025

Abstract: A nanotip apparatus which includes nanotips arranged in a pattern on a semiconductor base. Each of the nanotips have a pointed tip portion and a base portion in contact with the semiconductor base. Further, each of the nanotips include a gradient of silicon germanium (SiGe) with the highest concentration of germanium being at the pointed tip portion and the lowest concentration of germanium being at the base in contact with the semiconductor base. Also disclosed is a method in which the nanotips may be formed.

公开(公告)号：US09917199B2

公开(公告)日：2018-03-13

申请号：US15439078

申请日：2017-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/84 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.

公开(公告)号：US20170323952A1

公开(公告)日：2017-11-09

申请号：US15356979

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao LI ,  Xin Miao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/6681 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7853

Abstract: Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress liners provide a stress on the one or more channel structures. A gate is formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate. A source and drain region are formed on opposite sides of the gate.

公开(公告)号：US20170271525A1

公开(公告)日：2017-09-21

申请号：US15439078

申请日：2017-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L29/78618 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.

公开(公告)号：US09620641B2

公开(公告)日：2017-04-11

申请号：US15049796

申请日：2016-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Ali Khakifirooz ,  Alexander Reznicek ,  Soon-Cheon Seo

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

公开(公告)号：US09608067B2

公开(公告)日：2017-03-28

申请号：US14672311

申请日：2015-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Hong He ,  Juntao Li

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/28 ,  H01L29/161

CPC classification number: H01L29/1054 ,  H01L21/28026 ,  H01L21/28158 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.