公开(公告)号：US11387841B2

公开(公告)日：2022-07-12

申请号：US16650036

申请日：2017-12-15

Applicant: Intel IP Corporation

Inventor： Ofir Degani ,  Rotem Banin ,  Assaf Ben-Bassat ,  Bassam Khamaisi ,  Gil Asa

IPC: H03K5/13 ,  H03M1/82 ,  H03K5/01 ,  H03K5/00

Abstract: An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node. The apparatus additionally includes an interpolation circuit configured to weight the second interpolation signal based on a weighting factor, and to combine the first interpolation signal and the weighted second interpolation signal to generate a third interpolation signal.

公开(公告)号：US10768580B2

公开(公告)日：2020-09-08

申请号：US16474562

申请日：2017-03-02

Applicant: Intel IP Corporation

Inventor： Yair Dgani ,  Michael Kerner ,  Elan Banin ,  Evgeny Shumaker ,  Gil Horovitz ,  Ofir Degani ,  Rotem Banin ,  Aryeh Farber ,  Rotem Avivi ,  Eshel Gordon ,  Tami Sela

IPC: G04F7/08 ,  G04F10/00 ,  H03L7/085

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

公开(公告)号：US20190384230A1

公开(公告)日：2019-12-19

申请号：US16474562

申请日：2017-03-02

Applicant: Intel IP Corporation

Inventor： Yair Dgani ,  Michael Kerner ,  Elan Banin ,  Evgeny Shumaker ,  Gil Horovitz ,  Ofir Degani ,  Rotem Banin ,  Aryeh Farber ,  Rotem Avivi ,  Eshel Gordon ,  Tami Sela

IPC: G04F10/00 ,  H03L7/085

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

公开(公告)号：US09923563B1

公开(公告)日：2018-03-20

申请号：US15389520

申请日：2016-12-23

Applicant: Intel IP Corporation

Inventor： Gil Horovitz ,  Elan Banin ,  Igal Kushnir ,  Aryeh Farber ,  Ran Krichman ,  Ofir Degani ,  Rotem Banin

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03K5/1565 ,  H03L7/0805 ,  H03L7/085 ,  H03L2207/10

Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.

公开(公告)号：US09819479B2

公开(公告)日：2017-11-14

申请号：US14868834

申请日：2015-09-29

Applicant: Intel IP Corporation

Inventor： Ofir Degani ,  Rotem Banin ,  Sebastian Sievert

IPC: H04L27/36 ,  H04L7/00 ,  H03F3/24 ,  H03M1/68 ,  H03F3/217 ,  H03M1/82

CPC classification number: H04L7/002 ,  H03F3/2178 ,  H03F3/245 ,  H03M1/68 ,  H03M1/82 ,  H04L7/0091 ,  H04L27/365

Abstract: Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second and finer interpolation to increase interpolation ranges. The DTC circuitry generates a fine-phase modulated signal generating at least two correlated signals, and generating coarse and fine interpolations of the correlated signals.

公开(公告)号：US09806759B1

公开(公告)日：2017-10-31

申请号：US15200495

申请日：2016-07-01

Applicant: Intel IP Corporation

Inventor： Sebastian Sievert ,  Ofir Degani ,  Eshel Gordon

IPC: H04B1/04 ,  H04B1/40 ,  G05F3/26 ,  G05F3/20 ,  H04B1/62

CPC classification number: H04B1/40 ,  G05F1/613 ,  G05F3/205 ,  G05F3/26 ,  H03C3/00 ,  H04L27/361

Abstract: An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitry operatively coupled to the DTC circuitry, wherein a bias current of the LDO circuitry is adjustable; and logic circuitry operatively coupled to the LDO circuitry and DTC circuitry, wherein the logic circuitry is configured to set the adjustable bias current of the LDO circuitry according to a digital value input to the DTC circuitry.

公开(公告)号：US10972085B2

公开(公告)日：2021-04-06

申请号：US15811730

申请日：2017-11-14

Applicant: Intel IP Corporation

Inventor： Sebastian Sievert ,  Sarit Zur ,  Ofir Degani ,  Rotem Banin

IPC: H03K5/151 ,  H03K5/131 ,  H03K5/00 ,  H03M1/68 ,  H03M1/82

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.

公开(公告)号：US20180175842A1

公开(公告)日：2018-06-21

申请号：US15811730

申请日：2017-11-14

Applicant: Intel IP Corporation

Inventor： Sebastian Sievert ,  Sarit Zur ,  Ofir Degani ,  Rotem Banin

IPC: H03K5/151

CPC classification number: H03K5/1515 ,  H03K5/131 ,  H03K2005/00052 ,  H03M1/687 ,  H03M1/82

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.

公开(公告)号：US20180091177A1

公开(公告)日：2018-03-29

申请号：US15274509

申请日：2016-09-23

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Uri Parker ,  Ofir Degani ,  Michael Kerner

IPC: H04B1/04 ,  H04L27/36

CPC classification number: H04B1/0475 ,  H04B2001/0425 ,  H04L27/367

Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.

公开(公告)号：US09735952B2

公开(公告)日：2017-08-15

申请号：US14861132

申请日：2015-09-22

Applicant: Intel IP Corporation

Inventor： Ashoke Ravi ,  Ofir Degani ,  Rotem Banin ,  Assaf Ben-Bassat

IPC: H04B15/00 ,  H04L7/04 ,  H04L7/00 ,  H04B1/04 ,  G04F10/00 ,  H03K5/135 ,  H03M1/10 ,  H03M1/82

CPC classification number: H04L7/042 ,  G04F10/005 ,  H03K5/135 ,  H03M1/1061 ,  H03M1/82 ,  H04B1/0475 ,  H04L7/0054

Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.