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    Integrated circuit package for high bandwidth memory
    22.
    发明授权
    Integrated circuit package for high bandwidth memory 有权

    公开(公告)号：US11488944B2

    公开(公告)日：2022-11-01

    申请号：US17157278

    申请日：2021-01-25

    Applicant: Google LLC

    Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

    Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

    Integrated circuit substrate for containing liquid adhesive bleed-out
    24.
    发明授权
    Integrated circuit substrate for containing liquid adhesive bleed-out 有权

    公开(公告)号：US11264295B2

    公开(公告)日：2022-03-01

    申请号：US17038878

    申请日：2020-09-30

    Applicant: Google LLC

    Inventor： Woon Seong Kwon ,  Ryohei Urata ,  Teckgyu Kang

    IPC: H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

    Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

    DEEP TRENCH CAPACITORS EMBEDDED IN PACKAGE SUBSTRATE
    26.
    发明申请
    DEEP TRENCH CAPACITORS EMBEDDED IN PACKAGE SUBSTRATE 有权

    公开(公告)号：US20210273042A1

    公开(公告)日：2021-09-02

    申请号：US16806791

    申请日：2020-03-02

    Applicant: Google LLC

    Inventor： Nam Hoon Kim ,  Teckgyu Kang ,  Scott Lee Kirkman ,  Woon-Seong Kwon

    IPC: H01L49/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L25/16

    Abstract: This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.

    Integrated Circuit Substrate For Containing Liquid Adhesive Bleed-Out
    27.
    发明申请
    Integrated Circuit Substrate For Containing Liquid Adhesive Bleed-Out 有权

    公开(公告)号：US20210074601A1

    公开(公告)日：2021-03-11

    申请号：US17038878

    申请日：2020-09-30

    Applicant: Google LLC

    Inventor： Woon-Seong Kwon ,  Ryohei Urata ,  Teckgyu Kang

    IPC: H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

    Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

    MASSIVE DEEP TRENCH CAPACITOR DIE FILL FOR HIGH PERFORMANCE APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) APPLICATIONS
    28.
    发明申请
    MASSIVE DEEP TRENCH CAPACITOR DIE FILL FOR HIGH PERFORMANCE APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) APPLICATIONS 审中-公开

    公开(公告)号：US20200161235A1

    公开(公告)日：2020-05-21

    申请号：US16358197

    申请日：2019-03-19

    Applicant: Google LLC

    Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

    IPC: H01L23/522 ,  H01L49/02

    Abstract: A processor assembly and a system including a processor assembly are disclosed. The processor assembly includes an interposer disposed on a substrate, an integrated circuit disposed on the interposer, a memory circuit disposed on the interposer and coupled to the integrated circuit, and a capacitor embedded in the interposer. The capacitor includes at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure. The capacitor includes a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit. The capacitor includes a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit. The capacitor includes an oxide layer electrically isolating the capacitor from the interposer.

    Embedded air gap transmission lines
    29.
    发明授权
    Embedded air gap transmission lines 有权

    公开(公告)号：US10257921B1

    公开(公告)日：2019-04-09

    申请号：US15951717

    申请日：2018-04-12

    Applicant: Google LLC

    Inventor： Richard Roy ,  Pierre-luc Cantin ,  Teckgyu Kang ,  Woon Seong Kwon

    IPC: H05K1/02 ,  H01P3/08

    Abstract: Embedded air gap transmission lines and methods of fabrication are provided. An apparatus having an air gap transmission line can include a first conductive plane, a core dielectric layer having a bottom surface in contact with the first conductive plane, a conductor having a bottom surface in contact with a top surface of the core dielectric layer, and a second conductive plane positioned over, and spaced apart from, a top surface of the conductor such that a gap separates the conductor from the second conductive plane. The top surface of the conductor is separated from the bottom surface of the second conductive plane by a first distance measured along an axis normal to the first conductive plane, and the bottom surface of the conductor is separated from the first conductive plane by a second distance greater than the first distance measured along the axis.

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