Abstract:
A compliant interconnect with a cylindrical bellows structure is configured to reduce a stress between a substrate and a PCB board. The stress can be caused by a CTE (coefficient of thermal expansion) mismatch, a physical movement, or a combination thereof. The compliant interconnect can be solder to and/or immobilized on one or more coupling structure. Alternatively, the compliant interconnect can include an instant swapping structure (such as a socket) that makes the upgrade of the electronic components easier.
Abstract:
Embodiments of the present invention relate to nano-copper pillar interconnects. Nano-copper material is a mixture of nano-copper particles and one or more organic fluxes. In some embodiments, the one or more organic fluxes include organic solvents that help bind the nano-copper particles together and allow the nano-copper material to be printable. The nano-copper material is applied onto bond pads on a printed circuit board (PCB) via a printing process, a dipping process or the like, to form nano-copper covered PCB bond pads. A component can thereafter be coupled with the PCB at the nano-copper covered PCB bond pads. What is left when the solvents evaporate are nano-copper pillar interconnects that form, coupling the component with the PCB bond pads. The nano-copper pillar interconnects are of pure copper.
Abstract:
A formed graphite sheet is shaped and sized as a protective shield positioned over an electronic component coupled to a PCB. The formed graphite sheet is used to protect a body of the electronic component from heat applied during the assembly of the electronic component to the PCB, such as the heating steps used in SMT and through-hole technology. The formed graphite sheet is shaped to selective direct impinging heat. The heat can be directly away from the entire electronic component. Alternatively, the heat can be selectively directed away from some portions of the electronic component and toward other portions of the electronic component.
Abstract:
Two substrates are mechanically and electrically coupled together using a combination of a fast cure electrically non-conductive epoxy for mechanical attachment and a slow cure electrically conductive epoxy for electrical interconnects. The two epoxies are selectively applied between the two substrates as a stack, and the stack is subjected to a temperature that is sufficient to cure the fast cure electrically non-conductive epoxy in a short period of time but does not damage the substrates or components coupled thereto. In some applications, the temperature is less than 100 degrees Celsius and the time period is less than 5 seconds. The stack is removed from the heat and the slow cure electrically conductive epoxy continues to cure over a longer second period of time, such as a few hours to a day.
Abstract:
A method for making a Radio Frequency Identification (RFID) device on fabric is described herein. In a first example, an RFID semiconductor chip is attached to a piece of fabric. The RFID semiconductor chip includes two terminals. A solid wire is stitched into the fabric making an RFID antenna. The solid wire is attached to the terminals of the RFID semiconductor chip. In a second example, a metal wire is selected. The metal wire is stitched into fabric making an RFID antenna. The metal wire includes two ends and a conductive adhesive is applied to two ends of the metal wire. An RFID semiconductor chip is attached to the fabric. The RFID semiconductor chip includes two terminals and the RFID semiconductor chip is attached to the fabric at the two terminals. The conductive adhesive is cured. In both examples, the wire and the RFID semiconductor chip are encapsulated in fabric.
Abstract:
Embodiments of the present invention relate to a fixture design for pre-attachment package on package component assembly. The fixture design includes a plurality of pockets arranged in a N×M array. The plurality of pockets is sized to receive bottom packages. The fixture design includes global fiducials that are used to locate positions of the pockets on the fixture, and sets of local fiducials, with each set being specific to one of the pockets and used to refine the position of the location of a corresponding pocket. Each of the pockets can include one or more ear cuts for easy component placement and component removal. The fixture design can include a vacuum port for coupling with a vacuum source for drawing a vacuum to hold the bottom packages down. The fixture design can also include a cover that is used with the fixture to keep the components from being disturbed.
Abstract:
Methods of making a copper interconnect plated through hole assembly are disclosed. Nano copper ink dispersed in an organic solvent is able to be filled in the plated through hole and forming the copper interconnect by sintering at a temperature below the melting of the copper.
Abstract:
A method of and device for making a three dimensional electronic circuit. The method comprises coupling one or more magnet wires with a substrate along a surface contour of the substrate, immobilizing the one or more magnet wires on the substrate, and forming the electronic circuit by electrically coupling the one or more magnet wires with an integrated circuit chip.
Abstract:
An electronics assembly includes one or more electronic components coupled to a fabric. Each electronic component includes one or more electrical connection points, such as a bond pad or solder bump. The electronics assembly also includes one or more metal foils, one metal foil coupled to one electrical connection point on an electronic component. The metal foil is stitched to the fabric by an electrically conductive wire, thereby providing an electrical connection between the electronic component and the electrically conductive wire via the metal foil.
Abstract:
Methods of and Devices for quality control that can be used with automated optical inspection (AOI), solder paste inspection (SPI), and automated x-ray inspection (AXI) are disclosed. Plurality of threshold settings are entered in a testing process. Multiple testing results are obtained from the testing process. A graphic presentation is generated showing the numerical relationship among the data points, such that a quality control person is able to fine-tune the testing process to have a predetermined ratio of Defect Escaped % to False Call ppm.