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公开(公告)号：US08841969B2
公开(公告)日：2014-09-23
申请号：US13670016
申请日：2012-11-06
Inventor： Sang-Heung Lee , Seong-Il Kim , Dong Min Kang , Jong-Won Lim , Hyung Sup Yoon , Chull Won Ju , Jae Kyoung Mun , Eun Soo Nam
IPC: H03G3/12
CPC classification number: H03G1/0082 , H03G1/0088 , H03G3/3084
Abstract: Disclosed is an automatic gain control feedback amplifier that can arbitrarily control a gain even when a difference in input signal is large. The automatic gain control feedback amplifier includes: an amplification circuit unit configured to amplify voltage input from an input terminal and output the amplified voltage to an output terminal; a feedback circuit unit connected between the input terminal and the output terminal and including a feedback resistor unit of which a total resistance value is determined by one or more control signals and a feedback transistor connected to the feedback resistor unit in parallel; and a bias circuit unit configured to supply predetermined bias voltage to the feedback transistor.
Abstract translation: 公开了一种自动增益控制反馈放大器，其即使当输入信号的差异大时也可以任意地控制增益。 自动增益控制反馈放大器包括：放大电路单元，被配置为放大从输入端输入的电压，并将放大的电压输出到输出端; 连接在输入端子和输出端子之间的反馈电路单元，包括反馈电阻器单元，其总电阻值由一个或多个控制信号确定，反馈晶体管并联连接到反馈电阻器单元; 以及偏置电路单元，被配置为向所述反馈晶体管提供预定的偏置电压。
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公开(公告)号：US20140167070A1
公开(公告)日：2014-06-19
申请号：US13938324
申请日：2013-07-10
Inventor： Young Rak PARK , Sang Choon Ko , Byoung-Gue Min , Jong-Won Lim , Hokyun Ahn , Sung-Bum Bae , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H01L29/66477 , H01L23/5225 , H01L23/5228 , H01L23/5329 , H01L23/66 , H01L2223/6627 , H01L2223/6683 , H01L2924/0002 , H01L2924/00
Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.
Abstract translation: 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。
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公开(公告)号：US20140160689A1
公开(公告)日：2014-06-12
申请号：US13959666
申请日：2013-08-05
Inventor： Dong Min KANG , Chull Won Ju , Seong-Il Kim , Sang-Heung Lee , Jong-Won Lim , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
IPC: H05K1/02
CPC classification number: H01L23/66 , H01L23/49844 , H01L2223/6655 , H01L2224/48091 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
Abstract: A package includes a ground plate, a chip mounting plate disposed at a side of the ground plate and having a top surface lower than a top surface of the ground plate, a chip on the chip mounting plate, a first input/output terminal opposite to the chip mounting plate and disposed at another side of the ground plate, and a second input/output terminal opposite to the ground plate and disposed at a side of the chip mounting plate. The first and second input/output terminals are electrically connected to the chip.
Abstract translation: 一种封装，包括接地板，设置在接地板一侧的芯片安装板，具有比接地板的顶表面低的顶表面，芯片安装板上的芯片，与第一输入/输出端子相对的第一输入/输出端子 芯片安装板并且设置在接地板的另一侧，以及与接地板相对的第二输入/输出端子，并且设置在芯片安装板的一侧。 第一和第二输入/输出端子与芯片电连接。
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公开(公告)号：US20140159049A1
公开(公告)日：2014-06-12
申请号：US13905213
申请日：2013-05-30
Inventor： Sang Choon KO , Jae Kyoung Mun , Byoung-Gue Min , Young Rak Park , Hokyun Ahn , Jeong-Jin Kim , Eun Soo Nam
IPC: H01L29/66 , H01L29/808
CPC classification number: H01L29/808 , H01L21/76898 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/432 , H01L29/454 , H01L29/66462 , H01L29/7786
Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。
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25.发明申请IMPEDANCE MATCHING CIRCUIT, POWER AMPLIFIER AND MANUFACTURING METHOD FOR VARIABLE CAPACITOR 审中-公开阻抗匹配电路，功率放大器和可变电容器的制造方法公开(公告)号：US20130207730A1
公开(公告)日：2013-08-15
申请号：US13743667
申请日：2013-01-17
Inventor： Jongmin LEE , Byoung-Gue Min , Seong-Il Kim , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H01L21/8222 , H01G7/00 , H01L27/0647 , H01L27/0658 , H01L29/93 , H03F1/565 , H03F3/21 , H03F2200/36 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03H7/38 , Y10T29/43
Abstract: Disclosed is an impedance matching circuit capable of wideband matching. The impedance matching circuit includes: a first variable inductor unit of which one end is connected to the first node and an inductance value varies; a second inductor unit connected between the first node and a second node and having a variable inductance value; a first variable capacitor unit of which one end is connected to the first node and a capacitance value varies; and a second variable capacitor unit of which one end is connected to the second node and a capacitance value varies, and the other end of the first variable capacitor unit and the other end of the second variable capacitor unit are connected to a ground voltage terminal to perform the impedance matching between a circuit connected to the other end of the first variable inductor unit and a circuit connected to the second node.
Abstract translation: 公开了能够进行宽带匹配的阻抗匹配电路。 阻抗匹配电路包括：第一可变电感器单元，其一端连接到第一节点，电感值变化; 连接在第一节点和第二节点之间并具有可变电感值的第二电感器单元; 第一可变电容器单元，其一端连接到第一节点，电容值变化; 以及第二可变电容器单元，其一端连接到第二节点并且电容值变化，并且第一可变电容器单元的另一端和第二可变电容器单元的另一端连接到接地电压端子 执行连接到第一可变电感器单元的另一端的电路与连接到第二节点的电路之间的阻抗匹配。
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Patent Agency Ranking
公开(公告)号：US08937002B2
公开(公告)日：2015-01-20
申请号：US14230031
申请日：2014-03-31
Inventor： Sung Bum Bae , Eun Soo Nam , Jae Kyoung Mun , Sung Bock Kim , Hae Cheon Kim , Chull Won Ju , Sang Choon Ko , Jong-Won Lim , Ho Kyun Ahn , Woo Jin Chang , Young Rak Park
IPC: H01L21/20 , H01L29/66 , H01L21/8252 , H01L27/06 , H01L27/088 , H01L21/02
CPC classification number: H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。
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27.发明授权公开(公告)号：US08841154B2
公开(公告)日：2014-09-23
申请号：US13916006
申请日：2013-06-12
Inventor： Hyung Sup Yoon , Byoung-Gue Min , Jong-Won Lim , Ho Kyun Ahn , Jong Min Lee , Seong-il Kim , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H01L21/28008 , H01L21/28587 , H01L29/42316 , H01L29/66863
Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced. The method of manufacturing a field effect type compound semiconductor device includes: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa region in predetermined regions of the first oxide layer, the ohmic layer, and the active layer; planarizing the mesa region after forming a nitride layer by evaporating a nitride on the mesa region; forming an ohmic electrode on the first oxide layer; forming a minute gate resist pattern after forming a second oxide layer on a semiconductor substrate in which the ohmic electrode is formed and forming a minute gate pattern having a under-cut shaped profile by dry-etching the first oxide layer, the nitride layer, and the second oxide layer; forming a gate recess region by forming a head pattern of a gamma gate electrode on the semiconductor substrate; and forming the gamma gate electrode by evaporating refractory metal on the semiconductor substrate in which the gate recess region is formed.
Abstract translation: 公开了一种制造场效应型化合物半导体器件的方法，其中器件的漏电流降低并且击穿电压增强。 制造场效应型化合物半导体器件的方法包括：在衬底上堆叠有源层和欧姆层，并在欧姆层上形成第一氧化物层; 在所述第一氧化物层，所述欧姆层和所述有源层的预定区域中形成台面区域; 通过在台面区域上蒸发氮化物，在形成氮化物层之后使台面区域平坦化; 在所述第一氧化物层上形成欧姆电极; 在形成欧姆电极的半导体衬底上形成第二氧化物层之后形成微小栅极抗蚀剂图案，并通过干蚀刻第一氧化物层，氮化物层和形成具有下切形状轮廓的微小栅极图案 第二氧化物层; 通过在所述半导体衬底上形成伽马栅电极的头部图形来形成栅极凹部区域; 以及通过在形成有所述栅极凹部的所述半导体衬底上蒸发难熔金属而形成所述γ栅电极。
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公开(公告)号：US20140179088A1
公开(公告)日：2014-06-26
申请号：US13897706
申请日：2013-05-20
Inventor： Sung-Bum BAE , Sung Bock Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/02
CPC classification number: H01L21/0254 , H01L21/02458 , H01L21/02496 , H01L21/0262 , H01L21/02664 , H01L21/32
Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.
Abstract translation: 本发明构思提供了制造半导体衬底的方法。 该方法可以包括形成围绕衬底的边缘的停止图案，在除了停止图案之外的基板的整个顶表面上形成过渡层，以及在过渡层和停止图案上形成外延半导体层。 外延半导体层可能不会从停止图案生长。 也就是说，外延半导体层可以通过选择性各向同性生长方法从过渡层的顶表面和侧壁各向同性地生长，使得外延半导体层可以逐渐覆盖停止图案。
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公开(公告)号：US08759204B1
公开(公告)日：2014-06-24
申请号：US13897706
申请日：2013-05-20
Inventor： Sung-Bum Bae , Sung Bock Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/20
CPC classification number: H01L21/0254 , H01L21/02458 , H01L21/02496 , H01L21/0262 , H01L21/02664 , H01L21/32
Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.
Abstract translation: 本发明构思提供了制造半导体衬底的方法。 该方法可以包括形成围绕衬底的边缘的停止图案，在除了停止图案之外的基板的整个顶表面上形成过渡层，以及在过渡层和停止图案上形成外延半导体层。 外延半导体层可能不会从停止图案生长。 也就是说，外延半导体层可以通过选择性各向同性生长方法从过渡层的顶表面和侧壁各向同性地生长，使得外延半导体层可以逐渐覆盖停止图案。
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公开(公告)号：US20140167806A1
公开(公告)日：2014-06-19
申请号：US14020931
申请日：2013-09-09
Inventor： Chul Won JU , Hyung Sup Yoon , Jong-Won Lim , Sang-Heung Lee , Seong-il Kim , Dong Min Kang , Eun Soo Nam , Jae Kyoung Mun
IPC: G01R1/04
CPC classification number: G01R1/0466 , G01R1/0458
Abstract: Provided is a semiconductor device testing apparatus including a first socket configured to load a package, on which a semiconductor device to be tested may be mounted, and a second socket coupled to the first socket. The first socket may include an upper part including a hole configured to accommodate the package and a terminal pad provided at both side edges of the hole to hold input and output terminals of the package, and a lower part including a heating room, in which a heater and a temperature sensing part may be provided, the heater being configured to heat the semiconductor device and the temperature sensing part being configured to measure temperature of the semiconductor device. The second socket may include a probe card with a pattern that may be configured to receive test signals from an external power source.
Abstract translation: 提供一种半导体器件测试装置，包括：第一插座，被配置为加载可以安装待测试的半导体器件的封装，以及耦合到第一插座的第二插座。 第一插座可以包括上部，其包括被配置为容纳封装的孔和设置在孔的两个侧边缘处的端子垫，以保持封装的输入和输出端子，以及包括加热室的下部，其中 加热器和温度检测部件，加热器被配置为加热半导体器件，并且温度检测部分被配置为测量半导体器件的温度。 第二插座可以包括具有可被配置为从外部电源接收测试信号的模式的探针卡。
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