公开(公告)号：US06949407B2

公开(公告)日：2005-09-27

申请号：US11031265

申请日：2005-01-07

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf ,  Eng Meow Koon ,  Chua Swee Kwang ,  Huang Shuang Wu ,  Neo Yong Loo ,  Zhou Wei

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf ,  Eng Meow Koon ,  Chua Swee Kwang ,  Huang Shuang Wu ,  Neo Yong Loo ,  Zhou Wei

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/02 ,  H01L23/31 ,  H01L23/485 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract translation: 提供了用于封装晶圆级封装中集成电路芯片的系统和方法。 芯片的有源电路区域耦合到城堡块，并且根据实施例，输入/输出焊盘。 城堡块和输入/输出垫通过密封剂封装并保持就位。 当制造设备时，将城堡块和输入/输出垫片穿过。 如果需要，可以使其上制造器件的晶片部分变薄。 封装可以用作无引线芯片载体封装，或者可以堆叠在彼此之上。 当堆叠时，封装的相应触点优选地联接。 当芯片被激活时，可以将数据写入和从芯片接收。 可以通过将适当的信号或信号施加到适当的触点或触点来激活芯片。

公开(公告)号：US06894386B2

公开(公告)日：2005-05-17

申请号：US10118576

申请日：2002-04-08

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Eng Meow Koon ,  Ser Bok Leng ,  Chua Swee Kwang ,  So Chee Chung ,  Ho Kwok Seng

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Eng Meow Koon ,  Ser Bok Leng ,  Chua Swee Kwang ,  So Chee Chung ,  Ho Kwok Seng

IPC: H01L21/301 ,  H01L21/60 ,  H01L21/78 ,  H01L23/04 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/52 ,  H01L23/58

CPC classification number: H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/93 ,  H01L27/105 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/08237 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80898 ,  H01L2224/93 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

公开(公告)号：US08115306B2

公开(公告)日：2012-02-14

申请号：US12705277

申请日：2010-02-12

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Lou ,  Eng Meow Koon ,  Ser Bok Leng ,  Chun Swee Kwang ,  So Chee Chung ,  Ho Kwok Song

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Lou ,  Eng Meow Koon ,  Ser Bok Leng ,  Chun Swee Kwang ,  So Chee Chung ,  Ho Kwok Song

IPC: H01L23/48

CPC classification number: H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/93 ,  H01L27/105 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/08237 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80898 ,  H01L2224/93 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 一种装置包括集成电路管芯，其包括具有顶层，底层和在顶层和底层之间延伸的周边边缘表面的主体。 集成电路管芯还包括主体上的接合焊盘，外围边缘表面处的边缘接触以及将接合焊盘连接到边缘接触件的线。 边缘接触包括底面，其基本上在与包封模具的密封剂的表面相同的平面内。 公开了附加装置，系统和方法。

公开(公告)号：US20100068851A1

公开(公告)日：2010-03-18

申请号：US12624774

申请日：2009-11-24

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf ,  Eng Meow Koon ,  Chua Swee Kwang ,  Huang Shuang Wu ,  Neo Yong Loo ,  Zhou Wei

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf ,  Eng Meow Koon ,  Chua Swee Kwang ,  Huang Shuang Wu ,  Neo Yong Loo ,  Zhou Wei

IPC: H01L21/50

CPC classification number: H01L25/50 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract translation: 提供了用于封装晶圆级封装中集成电路芯片的系统和方法。 芯片的有源电路区域耦合到城堡块，并且根据实施例，输入/输出焊盘。 城堡块和输入/输出垫通过密封剂封装并保持就位。 当制造设备时，将城堡块和输入/输出垫片穿过。 如果需要，可以使其上制造器件的晶片部分变薄。 封装可以用作无引线芯片载体封装，或者可以堆叠在彼此之上。 当堆叠时，封装的相应触点优选地联接。 当芯片被激活时，可以将数据写入和从芯片接收。 可以通过将适当的信号或信号施加到适当的触点或触点来激活芯片。

公开(公告)号：US07358154B2

公开(公告)日：2008-04-15

申请号：US11281084

申请日：2005-11-17

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Eng Meow Koon ,  Ser Bok Leng ,  Chua Swee Kwang ,  So Chee Chung ,  Ho Kwok Seng

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Eng Meow Koon ,  Ser Bok Leng ,  Chua Swee Kwang ,  So Chee Chung ,  Ho Kwok Seng

IPC: H01L21/00

CPC classification number: H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/93 ,  H01L27/105 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/08237 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80898 ,  H01L2224/93 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

Abstract translation: 描述了在模具和边缘接触结构上形成边缘接触的方法。 模具上的边缘接触不会增加模具的高度。 边缘触点位于模具的周边。 边缘触点定位在锯木街道上。 每个边缘接触件连接到邻近锯街的每个模具的一个接合焊盘。 当模具分离时，边缘触点被分成每个相邻模具的触点。 在一个实施例中，在锯街道中形成凹部。 在一个实施例中，凹槽通过用机械切割器划线锯条形成。 将凹槽图案化并且沉积接触材料以形成边缘接触。

公开(公告)号：US07115984B2

公开(公告)日：2006-10-03

申请号：US10736244

申请日：2003-12-15

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L23/49805 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/00

Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.

Abstract translation: 公开了一种相对于X，Y和Z轴中的每一个基本上模具尺寸的半导体器件封装。 该包装件包括沿其至少一个周边边缘定位的外部连接器，并且基本上横跨周边边缘的高度延伸。 每个外部连接器通过在位于与封装的半导体器件的外周相邻的街道处切断基本上穿过基板坯料（例如硅晶片）的导电通孔来形成。 外部连接器可以包括至少部分地接收从支撑基板突出的导电柱的凹部。 组件可以包括堆叠布置的封装，而不增加高度的连接器。

公开(公告)号：US06790706B2

公开(公告)日：2004-09-14

申请号：US10285136

申请日：2002-10-30

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

IPC: H01L2144

CPC classification number: H01L25/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/85399 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

公开(公告)号：US06582992B2

公开(公告)日：2003-06-24

申请号：US10222294

申请日：2002-08-15

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

IPC: H01L2144

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07811 ,  H01L2924/00

Abstract: A stackable semiconductor package includes a semiconductor die, and has a chip sized peripheral outline matching that of the die. In addition to the die, the package includes stacking pads and stacking contacts on opposing sides of the die, and conductive grooves on the edges of the die in electrical communication with the stacking pads and the stacking contacts. The conductive grooves function as interlevel conductors for the package and can also function as edge contacts for the package. The configuration of the stacking pads, of the stacking contacts and of the conductive grooves permit multiple packages to be stacked and electrically interconnected to form stacked assemblies. A method for fabricating the package is performed at the wafer level on a substrate, such as a semiconductor wafer, containing multiple dice. In addition, multiple substrates can be stacked, bonded and singulated to form stacked assemblies that include multiple stacked packages.

Abstract translation: 可堆叠的半导体封装包括半导体管芯，并且具有与管芯相匹配的芯片尺寸的外围轮廓。 除了管芯之外，封装还包括在管芯的相对侧上的堆叠焊盘和堆叠触点，以及与堆叠焊盘和堆叠触点电连通的管芯边缘上的导电槽。 导电槽用作封装的层间导体，并且还可以用作封装的边缘触点。 堆叠焊盘，堆叠触点和导电沟槽的配置允许多个封装堆叠并电互连以形成堆叠的组件。 用于制造封装的方法在晶片级上在诸如半导体晶片的基板上进行，该半导体晶片包含多个管芯。 此外，可以堆叠，粘合和分割多个基板以形成包括多个堆叠封装的堆叠组件。

公开(公告)号：US07285850B2

公开(公告)日：2007-10-23

申请号：US11430375

申请日：2006-05-08

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L23/49805 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/00

Abstract: A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding from the support substrate. The at least one conductive column is configured to contact an outer connector on a peripheral edge of a semiconductor device that may be carried by the support structure. Optionally, the at least one conductive column may engage a feature of (e.g., a recess in) the peripherally disposed outer connector. The at least one conductive column may facilitate alignment of one or more semiconductor devices with the support substrate alignment of semiconductor devices relative to one another, or electrical connection between multiple semiconductor devices of other components.

Abstract translation: 具有外围设置的触点的半导体器件的支撑结构包括支撑衬底和从支撑衬底突出的至少一个导电柱。 所述至少一个导电柱构造成接触可由所述支撑结构承载的半导体器件的外围边缘上的外部连接器。 可选地，至少一个导电柱可以接合外围设置的外部连接器（例如，凹部）的特征。 所述至少一个导电柱可以促进一个或多个半导体器件与半导体器件相对于彼此的支撑衬底对准或其它部件的多个半导体器件之间的电连接的对准。

公开(公告)号：US06747348B2

公开(公告)日：2004-06-08

申请号：US09981948

申请日：2001-10-16

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

IPC: H01L2302

CPC classification number: H01L25/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/85399 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.