Invention Grant
- Patent Title: Apparatus and method for leadless packaging of semiconductor devices
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Application No.: US10285136Application Date: 2002-10-30
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Publication No.: US06790706B2Publication Date: 2004-09-14
- Inventor: Boon Suan Jeung , Chia Yong Poo , Low Siu Waf
- Applicant: Boon Suan Jeung , Chia Yong Poo , Low Siu Waf
- Main IPC: H01L2144
- IPC: H01L2144

Abstract:
The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.
Public/Granted literature
- US20030080403A1 Apparatus and method for leadless packaging of semiconductor devices Public/Granted day:2003-05-01
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