公开(公告)号：US20170018652A1

公开(公告)日：2017-01-19

申请号：US15122066

申请日：2016-02-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng LIU ,  Xiaoyong LU ,  Xiaolong LI ,  Yu-Cheng CHAN

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78621 ,  H01L27/02 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78696

Abstract: A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.

Abstract translation: 提供了制造多晶硅薄膜晶体管的方法。 该方法包括形成多晶硅有源层，顺序地在有源层上形成第一栅极绝缘层和第一栅电极，通过使用第一栅电极作为掩模在有源层上进行第一离子注入工艺以形成两个掺杂区域 在有源层的端部，顺序地在第一栅极绝缘层和第一栅电极上形成第二栅极绝缘层和第二栅电极，并且通过使用第二栅电极作为另一栅电极在有源层上进行第二离子注入工艺 掩模以在有源层的掺杂区域的两个外侧形成两个源极/漏极注入区域。 因此，两个掺杂区域的杂质浓度小于两个源极/漏极注入区域的杂质浓度。

公开(公告)号：US20230359090A1

公开(公告)日：2023-11-09

申请号：US17312306

申请日：2020-12-30

Applicant: Beijing BOE Display Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Chunguang TIAN ,  Tianyu XIA ,  Xiaolong LI

IPC: G02F1/1343 ,  G02F1/1333 ,  G02F1/1362

CPC classification number: G02F1/134309 ,  G02F1/133345 ,  G02F1/136286

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a display region and a peripheral region surrounding the display region, and includes: a common electrode line extending in a first direction on a base substrate and arranged at the display region and the peripheral region; a first conductive pattern arranged at the peripheral region and electrically connected to the common electrode line; an insulation layer covering the first conductive pattern and the common electrode line, a via-hole being formed in the insulation layer, an orthogonal projection of the via-hole onto the base substrate not overlapping an orthogonal projection of the common electrode line onto the base substrate; and a second conductive pattern arranged at the peripheral region and at a side of the insulation layer distal to the first conductive pattern, and electrically connected to the first conductive pattern through the via-hole.

公开(公告)号：US20210043701A1

公开(公告)日：2021-02-11

申请号：US16965920

申请日：2019-12-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Dong LI ,  Hongwei TIAN ,  Chunyang WANG ,  Huijuan ZHANG ,  Zheng LIU ,  Xiaolong LI ,  Meng ZHAO ,  Mingche HSIEH

IPC: H01L27/32 ,  G09G3/3225

Abstract: A flexible display panel has a display area, a peripheral area surrounding the display area, and a bending area having at least one overlapping area with the peripheral area. The flexible display panel includes a plurality of conductive layers disposed in the display area, and at least one interdigital capacitor disposed in the at least one overlapping area. One of the at least one interdigital capacitor is disposed in a same layer with a same material as one of the plurality of conductive layers.

公开(公告)号：US20200302867A1

公开(公告)日：2020-09-24

申请号：US16769420

申请日：2019-11-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xueling GAO ,  Kuanjun PENG ,  Wei QIN ,  Zhiqiang XU ,  Tieshi WANG ,  Xiaolong LI ,  Jintao PENG

IPC: G09G3/3258 ,  G09G3/3275

Abstract: A pixel driving circuit and a driving method thereof, and a display panel are provided. The pixel driving circuit includes a driving sub-circuit, a reset sub-circuit, a light-emitting control sub-circuit, and a first compensation sub-circuit, the reset sub-circuit, the light-emitting control sub-circuit, and the first compensation sub-circuit are configured to, in an initialization phase, under control of a first driving signal and a second driving signal, provide the first power supply voltage provided by the first power supply input terminal to the control terminal of the driving sub-circuit; the first terminal of the driving sub-circuit is connected to the second power supply input terminal to receive the second power supply voltage; and the first power supply voltage and the second power supply voltage are configured to cause the driving sub-circuit to be in an on-bias state in the initialization phase.

公开(公告)号：US20200226965A1

公开(公告)日：2020-07-16

申请号：US16482107

申请日：2018-09-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yanhui XI ,  Bin DAI ,  Xiaomang ZHANG ,  Yan SUN ,  Kuanjun PENG ,  Haijun NIU ,  Xiaolong LI ,  Donghui WANG

IPC: G09G3/20

Abstract: Disclosed is a primary color conversion method, which may expand primary color signals that are applicable to a display device. The primary color conversion method includes: acquiring color coordinates and a brightness value of a first color in a first color gamut having M primary colors according to gray-scale values of the M primary colors corresponding to the first color; and mapping the color coordinates and the luminance value of the first color in the first color gamut to color coordinates and a brightness value of a second color corresponding to the first color in a second color gamut having N primary colors. 3≤M, 3≤N, M is different from N, and M and N are positive integers.

公开(公告)号：US20190219917A1

公开(公告)日：2019-07-18

申请号：US16106155

申请日：2018-08-21

Applicant: BOE Technology Group Co., Ltd. ,  Beijing BOE Display Technology Co., Ltd.

Inventor： Xiaoxiang ZHANG ,  Huibin GUO ,  Yongzhi SONG ,  Mingxuan LIU ,  Wenqing XU ,  Xiaolong LI ,  Zumou WU

IPC: G03F1/44

CPC classification number: G03F1/44 ,  G02F1/136286 ,  G02F2001/136295

Abstract: Disclosed are a mask, a display substrate and a display device. The mask comprises a substrate, a first exposure structure, a second exposure structure located at one side of the substrate and disposed opposite to each other, the first exposure structure comprises a first light transmission film layer and a first light shielding film layer, an orthographic projection of the first light shielding film layer falls within an orthographic projection of the first light transmission film layer on the substrate; the second exposure structure comprises a second light transmission film layer and a second light shielding film layer, an orthographic projection of the second light shielding film layer falls within an orthographic projection of the second light transmission film layer on the substrate; a side edge of the first exposure structure has a first zigzag structure, and a side edge of the second exposure structure has a second zigzag structure.

公开(公告)号：US20180197996A1

公开(公告)日：2018-07-12

申请号：US15528215

申请日：2016-12-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng LIU ,  Xiaolong LI ,  Yueping ZUO ,  Lujiang HUANGFU

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L29/66757 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78696

Abstract: A semiconductor device, an array substrate, and a display device, and their fabrication methods are provided. An exemplary semiconductor device includes a first electrode, an insulating layer, and a second electrode, over a substrate. A conductive layer is on the insulating layer. A semiconductor layer is on the first electrode, on a first sidewall of the insulating layer, on the conductive layer, on the second sidewall of the insulating layer, and on the second electrode. A first gate electrode is over a portion of the semiconductor layer that is on the first sidewall of the insulating layer. A second gate electrode is over a portion of the semiconductor layer that is on the second sidewall of the insulating layer.

公开(公告)号：US20180138254A1

公开(公告)日：2018-05-17

申请号：US15519313

申请日：2016-11-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Zheng LIU ,  Xiaolong LI ,  Lujiang HUANG FU

IPC: H01L27/32 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L21/02 ,  H01L21/311 ,  G02F1/1368

CPC classification number: H01L27/3262 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31133 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/127 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78636 ,  H01L29/78642 ,  H01L29/78675 ,  H01L29/78696 ,  H01L2227/323

Abstract: The disclosed subject matter provides a thin film transistor and a fabricating method thereof. The thin film transistor includes a substrate, a source electrode and a drain electrode on the substrate, an active layer on the source and drain electrodes, a gate insulating layer on the active layer, and a gate electrode on the gate insulating layer. The active layer extends from the source electrode towards the drain electrode along a non-linear path.

公开(公告)号：US20160307978A1

公开(公告)日：2016-10-20

申请号：US14785777

申请日：2015-03-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng LIU ,  Xiaoyong LU ,  Xiaolong LI ,  Chien Hung LIU ,  Chunping LONG

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52

CPC classification number: H01L27/3262 ,  H01L27/1248 ,  H01L27/1274 ,  H01L27/1285 ,  H01L27/3246 ,  H01L51/5206 ,  H01L51/5221 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/558

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The manufacturing method of the array substrate comprises: forming a first conductive thin film (100) on a base substrate (1); and patterning the first conductive thin film (100), to form a pattern of a cathode (11) on a first region (11) of the base substrate (1), and form a pattern of a gate electrode (4) on a second region (12) of the base substrate (1). Complexity and process time of a fabrication process of an array substrate can be reduced, a fabrication process of an organic electroluminescent panel can be simplified, and production cost can be reduced, by forming a cathode layer of a light-emitting diode and a gate electrode layer of a thin film transistor in different regions of the base substrate at the same time by one patterning process.

Abstract translation: 提供阵列基板，阵列基板和显示装置的制造方法。 阵列基板的制造方法包括：在基底（1）上形成第一导电薄膜（100）; 以及图案化所述第一导电薄膜（100），以在所述基底基板（1）的第一区域（11）上形成阴极（11）的图案，并在第二导电薄膜（1）上形成栅电极（4）的图案 基底（1）的区域（12）。 可以减少阵列基板的制造工艺的复杂性和处理时间，通过形成发光二极管和栅电极的阴极层，可以简化有机电致发光面板的制造工艺，并且可以降低生产成本 通过一个图案化工艺同时在基底基板的不同区域中的薄膜晶体管层。

公开(公告)号：US20160254389A1

公开(公告)日：2016-09-01

申请号：US14768349

申请日：2015-03-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong LU ,  Zheng LIU ,  Liang SUN ,  Xiaolong LI ,  Chunping LONG

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/285 ,  H01L27/12

CPC classification number: H01L29/78618 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/1222 ,  H01L27/1274 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696

Abstract: A low temperature poly-silicon thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The method comprises: S1: sequentially forming an active layer (3), a gate insulation layer (4), a gate electrode (5) and an interlayer insulation layer (6) on a base substrate (1); S2: forming a first metal thin film layer (8); S3: performing a hydrogenation treatment on the active layer (3) and the gate insulation layer (6); S4: forming a second metal thin film layer (7), the second metal thin film layer (7) being used for forming a source electrode and a drain electrode.

Abstract translation: 提供一种低温多晶硅薄膜晶体管及其制造方法，阵列基板和显示装置。 该方法包括：S1：在基底（1）上依次形成有源层（3），栅极绝缘层（4），栅电极（5）和层间绝缘层（6）; S2：形成第一金属薄膜层（8）; S3：在有源层（3）和栅极绝缘层（6）上进行氢化处理; S4：形成第二金属薄膜层（7），第二金属薄膜层（7）用于形成源电极和漏电极。