Plasma processing method and apparatus with control of rf bias
    21.
    发明授权
    Plasma processing method and apparatus with control of rf bias 有权
    等离子体处理方法和控制rf偏差的装置

    公开(公告)号:US06265831B1

    公开(公告)日:2001-07-24

    申请号:US09281808

    申请日:1999-03-31

    IPC分类号: H01J724

    摘要: A tendency for a discontinuity to occur in the amount of power reflected back to an r.f. bias source of a vacuum plasma processor is overcome by controlling the r.f. bias source output power so the power delivered to plasma in a vacuum processing chamber remains substantially constant. The r.f bias source output power is changed much faster than changes in capacitors of a matching network connecting the r.f. bias power source to an electrode of a workpiece holder processor. A capacitive impedance component of the plasma is determined by optically measuring the thickness of a plasma sheath in the chamber.

    摘要翻译: 在反映到r.f.的功率量中发生不连续的趋势。 通过控制r.f.克服了真空等离子体处理器的偏压源。 偏压源输出功率,使得在真空处理室中输送到等离子体的功率基本保持不变。 r.f偏置源输出功率的改变比连接r.f的匹配网络的电容器的变化快得多。 偏压电源到工件支架处理器的电极。 通过光学测量腔室中的等离子体护套的厚度来确定等离子体的电容性阻抗分量。

    Line guide for fishing rod
    22.
    发明授权
    Line guide for fishing rod 失效
    钓鱼竿导轨

    公开(公告)号:US4186508A

    公开(公告)日:1980-02-05

    申请号:US960701

    申请日:1978-11-14

    申请人: Arthur M. Howald

    发明人: Arthur M. Howald

    IPC分类号: A01K87/04 B32B9/00

    摘要: A line guide for a fishing rod having a circular laminate (14) of resin-impregnated graphite fibers and a linear foot laminate (13) of resin-impregnated graphite fibers. The foot is attached to the circular laminate by winding some of the fibers (14) of the circular laminate underlying the foot and others (14') overlying the foot, and then heat-curing the assembly to produce a monolithic line guide and foot structure (12).

    摘要翻译: 一种用于具有树脂浸渍的石墨纤维的圆形层压板(14)和浸渍有树脂的石墨纤维的直线脚踏板(13)的钓鱼杆的导轨。 通过缠绕脚底部的圆形层压体的一些纤维(14)和覆盖脚的其他(14')将足部附接到圆形层压体上,然后热固化组件以产生整体式导线和脚部结构 (12)。

    Method of determining the correct average bias compensation voltage during a plasma process
    23.
    发明授权
    Method of determining the correct average bias compensation voltage during a plasma process 有权
    在等离子体工艺期间确定正确的平均偏置补偿电压的方法

    公开(公告)号:US07583492B2

    公开(公告)日:2009-09-01

    申请号:US11725772

    申请日:2007-03-19

    申请人: Arthur M. Howald

    发明人: Arthur M. Howald

    IPC分类号: H01T23/00

    CPC分类号: H01L21/6831

    摘要: A method for removing a substrate that is attached to a bipolar electrostatic chuck (ESC) by application of a bipolar ESC voltage is provided which includes discontinuing the bipolar ESC voltage after processing a current substrate, and determining a monopolar component error of the processing. The method also includes correcting the monopolar component error for a subsequent substrate.

    摘要翻译: 提供了一种通过施加双极性ESC电压来除去附着在双极静电卡盘(ESC)上的基板的方法,该方法包括在处理当前基板之后停止双极性ESC电压,并确定处理的单极分量误差。 该方法还包括校正后续衬底的单极分量误差。

    Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide
    25.
    发明申请
    Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide 有权
    用于工程化硅型表面以进行选择性金属沉积以形成金属硅化物的工艺和系统

    公开(公告)号:US20070292615A1

    公开(公告)日:2007-12-20

    申请号:US11513446

    申请日:2006-08-30

    摘要: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve silicon-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce a silicon-to-metal interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a layer of a metal on a silicon or polysilicon surface of the substrate to form a metal silicide in an integrated system is provided. The method includes removing organic contaminants from the substrate surface in the integrated system, and reducing the silicon or polysilicon surface in the integrated system after removing organic contaminants to convert silicon oxide on the silicon or polysilicon surface to silicon, wherein after reducing the silicon or polysilicon surface, the substrate is transferred and processed in controlled environment to prevent the formation of silicon oxide, the silicon or polysilicon surface is reduced to increase the selectivity of the metal on the silicon surface. The method further includes selectively depositing the layer of the metal on the silicon or polysilicon surface of substrate in the integrated system after reducing the silicon or polysilicon surface. An exemplary system to practice the exemplary method described above is also provided.

    摘要翻译: 这些实施方案通过提供产生硅 - 金属界面的改进的工艺和系统来满足增强电迁移性能,提供较低金属电阻率以及改进铜互连的硅 - 金属界面粘附的需要。 提供了制备衬底的衬底表面以在衬底的硅或多晶硅表面上选择性地沉积金属层以在集成系统中形成金属硅化物的示例性方法。 该方法包括从集成系统中的衬底表面去除有机污染物,以及在去除有机污染物之后减少集成系统中的硅或多晶硅表面,以将硅或多晶硅表面上的氧化硅转化为硅,其中在还原硅或多晶硅之后 表面,在受控环境中转移和处理衬底以防止形成氧化硅,减少硅或多晶硅表面以增加金属在硅表面上的选择性。 该方法还包括在减少硅或多晶硅表面之后,在集成系统中的衬底的硅或多晶硅表面上选择性地沉积金属层。 还提供了用于实践上述示例性方法的示例性系统。

    Processes and systems for engineering a barrier surface for copper deposition
    26.
    发明申请
    Processes and systems for engineering a barrier surface for copper deposition 有权
    用于工程用于铜沉积的阻挡面的工艺和系统

    公开(公告)号:US20070292603A1

    公开(公告)日:2007-12-20

    申请号:US11514038

    申请日:2006-08-30

    摘要: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect. The method also includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method further includes depositing the thin copper seed layer in the integrated system, and depositing a gap-fill copper layer over the thin copper seed layer in the integrated system. An exemplary system to practice the exemplary method described above is also provided.

    摘要翻译: 这些实施方案通过提供改进的工艺和系统来提供改进的金属 - 金属界面,更具体地说是阻隔层,提高了电迁移性能,提供较低的金属电阻率,以及改进铜互连的金属 - 金属界面粘附的需要, 到铜接口。 一种制备衬底的衬底表面的示例性方法,以沉积金属阻挡层以对衬底的铜互连结构进行排列并且在集成系统中在金属阻挡层的表面上沉积薄铜籽晶层以改善电迁移性能 的铜互连。 该方法包括清洁底层金属的暴露表面以去除集成系统中的表面金属氧化物,其中下面的金属是与铜互连电连接的底层互连件的一部分。 该方法还包括沉积金属阻挡层以在集成系统中对铜互连结构进行排列,其中在沉积金属阻挡层之后,将基底在受控环境中转移和加工以防止形成金属阻挡氧化物。 该方法还包括在集成系统中沉积薄铜籽晶层,以及在集成系统中的薄铜籽晶层上沉积间隙填充铜层。 还提供了用于实践上述示例性方法的示例性系统。

    Method of determining the correct average bias compensation voltage during a plasma process
    27.
    发明授权
    Method of determining the correct average bias compensation voltage during a plasma process 有权
    在等离子体工艺期间确定正确的平均偏置补偿电压的方法

    公开(公告)号:US07218503B2

    公开(公告)日:2007-05-15

    申请号:US10882837

    申请日:2004-06-30

    申请人: Arthur M. Howald

    发明人: Arthur M. Howald

    IPC分类号: H01H3/00

    摘要: A method for removing a substrate that is attached to a bipolar electrostatic chuck (ESC) by application of a bipolar ESC voltage is provided which includes discontinuing the bipolar ESC voltage after processing a current substrate, and determining a monopolar component error of the processing. The method also includes correcting the monopolar component error for a subsequent substrate.

    摘要翻译: 提供了一种通过施加双极性ESC电压来除去附着在双极静电卡盘(ESC)上的基板的方法,该方法包括在处理当前基板之后停止双极性ESC电压,并确定处理的单极分量误差。 该方法还包括校正后续衬底的单极分量误差。

    High sputter, etch resistant window for plasma processing chambers
    28.
    发明授权
    High sputter, etch resistant window for plasma processing chambers 失效
    用于等离子体处理室的高溅射,耐蚀刻窗口

    公开(公告)号:US6074516A

    公开(公告)日:2000-06-13

    申请号:US103357

    申请日:1998-06-23

    摘要: A window of a plasma processing chamber. The window includes a first dielectric portion having a first electrical thickness and a first resistivity to an etching plasma that is formed within the plasma processing chamber. There is further included a second dielectric portion disposed within the first dielectric portion. The second dielectric portion has a second electrical thickness that is less than the first electrical thickness. The second dielectric portion is formed of a substantially transparent material and has a second resistivity to the etching plasma. The second resistivity is higher than the first resistivity.

    摘要翻译: 等离子体处理室的窗口。 窗口包括具有第一电气厚度和形成在等离子体处理室内的蚀刻等离子体的第一电阻率的第一电介质部分。 还包括设置在第一电介质部分内的第二电介质部分。 第二电介质部分具有小于第一电气厚度的第二电气厚度。 第二电介质部分由基本上透明的材料形成,并且对蚀刻等离子体具有第二电阻率。 第二电阻率高于第一电阻率。