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    CMOS over array of 3-D DRAM device
    21.
    发明授权
    CMOS over array of 3-D DRAM device 有权

    公开(公告)号：US11980021B2

    公开(公告)日：2024-05-07

    申请号：US17829939

    申请日：2022-06-01

    Applicant: Applied Materials, Inc.

    Inventor： Sony Varghese ,  Fred Fishburn

    IPC: H10B12/00

    CPC classification number: H10B12/09 ,  H10B12/03 ,  H10B12/05 ,  H10B12/30 ,  H10B12/50

    Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

    LOCALIZED STRESS MODULATION BY IMPLANT TO BACK OF WAFER
    23.
    发明申请
    LOCALIZED STRESS MODULATION BY IMPLANT TO BACK OF WAFER 有权

    公开(公告)号：US20220344171A1

    公开(公告)日：2022-10-27

    申请号：US17396101

    申请日：2021-08-06

    Applicant: Applied Materials, Inc.

    Inventor： Sony Varghese ,  Pradeep Subrahmanyan ,  Dennis Rodier ,  Kyuha Shim

    IPC: H01L21/3115 ,  H01L21/66 ,  H01J37/317 ,  H01J37/304 ,  H01J37/147

    Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

    CMOS over array of 3-D DRAM device
    24.
    发明授权
    CMOS over array of 3-D DRAM device 有权

    公开(公告)号：US11380691B1

    公开(公告)日：2022-07-05

    申请号：US17230591

    申请日：2021-04-14

    Applicant: Applied Materials, Inc.

    Inventor： Sony Varghese ,  Fred Fishburn

    IPC: H01L27/108

    Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

    FIN DAMAGE REDUCTION DURING PUNCH THROUGH IMPLANTATION OF FINFET DEVICE
    26.
    发明申请
    FIN DAMAGE REDUCTION DURING PUNCH THROUGH IMPLANTATION OF FINFET DEVICE 审中-公开

    公开(公告)号：US20200152735A1

    公开(公告)日：2020-05-14

    申请号：US16186027

    申请日：2018-11-09

    Applicant: APPLIED Materials, Inc.

    Inventor： Min Gyu Sung ,  Jae Young Lee ,  Johannes Van Meer ,  Sony Varghese ,  Naushad K. Variam

    IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762

    Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.

    3-D DRAM WORDLINE PARTITION AND STAIRCASE CONTACTS
    28.
    发明申请
    3-D DRAM WORDLINE PARTITION AND STAIRCASE CONTACTS 有权

    公开(公告)号：US20250126774A1

    公开(公告)日：2025-04-17

    申请号：US18403930

    申请日：2024-01-04

    Applicant: Applied Materials, Inc.

    Inventor： Chang Seok Kang ,  Sony Varghese ,  Tong Liu ,  Fredrick Fishburn

    IPC: H10B12/00

    Abstract: Memory devices are provided which have stacked DRAM cells, resulting in an increase in DRAM cell bit-density. In a 3D DRAM with stacked unit cell layers of one or more embodiments, it is necessary to reduce the area of a unit cell in order to increase bit density per unit area for a given number of stacked cells. In one or more embodiments, n wordlines (nWL, n is an integer≥2) share a contact pad. The shared nWLs are separated by n bitlines (BLs) to assign every cell independently one WL and one BL.

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