公开(公告)号：US20250140569A1

公开(公告)日：2025-05-01

申请号：US19007772

申请日：2025-01-02

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  Pradeep Subrahmanyan ,  Dennis Rodier ,  Kyuha Shim

IPC: H01L21/3115 ,  H01J37/147 ,  H01J37/304 ,  H01J37/317 ,  H01L21/66

Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

公开(公告)号：US12217974B2

公开(公告)日：2025-02-04

申请号：US17396101

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  Pradeep Subrahmanyan ,  Dennis Rodier ,  Kyuha Shim

IPC: H01L21/3115 ,  H01J37/147 ,  H01J37/304 ,  H01J37/317 ,  H01L21/66

Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

公开(公告)号：US11700721B2

公开(公告)日：2023-07-11

申请号：US17477858

申请日：2021-09-17

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese

IPC: H10B12/00 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H10B12/053 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/308 ,  H01L21/3065 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/488

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

公开(公告)号：US11569242B2

公开(公告)日：2023-01-31

申请号：US17238572

申请日：2021-04-23

Applicant: APPLIED Materials, Inc.

Inventor： Sony Varghese ,  Min Gyu Sung

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/417 ,  H01L21/311 ,  H01L21/308

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

公开(公告)号：US20220093458A1

公开(公告)日：2022-03-24

申请号：US17028259

申请日：2020-09-22

Applicant: Applied Materials, Inc.

Inventor： M. Arif Zeeshan ,  Kelvin Chan ,  Shantanu Kallakuri ,  Sony Varghese ,  John Hautala

IPC: H01L21/768 ,  H01L21/48

Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such as transistors, dual work function stacks, dynamic random-access memory (DRAM), non-volatile memory, and the like.

公开(公告)号：US20220005812A1

公开(公告)日：2022-01-06

申请号：US17477858

申请日：2021-09-17

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/265

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

公开(公告)号：US11018138B2

公开(公告)日：2021-05-25

申请号：US16664107

申请日：2019-10-25

Applicant: APPLIED Materials, Inc.

Inventor： Sony Varghese ,  Min Gyu Sung

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/417 ,  H01L21/311

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

公开(公告)号：US11974423B2

公开(公告)日：2024-04-30

申请号：US17551903

申请日：2021-12-15

Applicant: Applied Materials, Inc.

Inventor： Fredrick Fishburn ,  Arvind Kumar ,  Sony Varghese

IPC: H10B12/00

CPC classification number: H10B12/05 ,  H10B12/03

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

公开(公告)号：US20230369112A1

公开(公告)日：2023-11-16

申请号：US18224904

申请日：2023-07-21

Applicant: Applied Materials, Inc.

Inventor： M. Arif Zeeshan ,  Kelvin Chan ,  Shantanu Kallakuri ,  Sony Varghese ,  John Hautala

IPC: H01L21/768 ,  H01L21/48

CPC classification number: H01L21/76879 ,  H01L21/486

Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such as transistors, dual work function stacks, dynamic random-access memory (DRAM), non-volatile memory, and the like.

公开(公告)号：US11557515B2

公开(公告)日：2023-01-17

申请号：US16989019

申请日：2020-08-10

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese

IPC: H01L21/768

Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include providing a plurality of patterning structures over a device layer, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface, and forming a mask by depositing a masking material at a non-zero angle of inclination relative to a perpendicular to a plane defined by a top surface of the device layer. The mask may be formed over the plurality of patterning structures without being formed along the second sidewall. The method may further include selectively forming a metal layer along the second sidewall of each of the plurality of patterning structures.