公开(公告)号：US5274601A

公开(公告)日：1993-12-28

申请号：US972545

申请日：1992-11-06

Applicant: Takayuki Kawahara ,  Yoshiki Kawajiri ,  Takesada Akiba ,  Masashi Horiguchi ,  Takao Watanabe ,  Goro Kitsukawa ,  Yasushi Kawase ,  Toshikazu Tachibana ,  Masakazu Aoki

Inventor： Takayuki Kawahara ,  Yoshiki Kawajiri ,  Takesada Akiba ,  Masashi Horiguchi ,  Takao Watanabe ,  Goro Kitsukawa ,  Yasushi Kawase ,  Toshikazu Tachibana ,  Masakazu Aoki

IPC: G11C11/40 ,  G11C5/14 ,  G11C8/08 ,  H01L27/02 ,  H01L27/06 ,  H03K19/00 ,  G11C8/00

CPC classification number: H03K19/0016 ,  G11C5/14 ,  G11C8/08

Abstract: A device parameter of a switching transistor is set in such a way that a leakage current of the switching transistor making up a power source switch which is turned off in a stand-by state is smaller than the sum total of subthreshold currents of P-channel or N-channel MOS transistors in an off state of a plurality of CMOS circuits. Therefore, the currents which flow through the plurality of CMOS circuits in the stand-by state are not determined by the subthreshold current but are determined by a small leakage current of the switching transistor. As a result, even when the CMOS circuit is shrunken and the subthreshold current increases, it is possible to reduce the current consumption in the stand-by state.

Abstract translation: 开关晶体管的器件参数被设置为使得构成在待机状态下被截止的电源开关的开关晶体管的漏电流小于P沟道的亚阈值电流的总和 或多个CMOS电路处于断开状态的N沟道MOS晶体管。 因此，在待机状态下流过多个CMOS电路的电流不由亚阈值电流确定，而是由开关晶体管的小的漏电流确定。 结果，即使当CMOS电路收缩并且亚阈值电流增加时，也可以减少待机状态下的电流消耗。

公开(公告)号：US5165009A

公开(公告)日：1992-11-17

申请号：US634046

申请日：1990-12-26

Applicant: Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

Inventor： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC: G06F15/18 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00

CPC classification number: G06N3/063

Abstract: Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; and input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the otuput in parallel.

公开(公告)号：US4984202A

公开(公告)日：1991-01-08

申请号：US496238

申请日：1990-03-20

Applicant: Takayuki Kawahara ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Kiyoo Itoh

Inventor： Takayuki Kawahara ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Kiyoo Itoh

IPC: G11C11/409 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4074 ,  H01L27/10 ,  H03K19/0175

CPC classification number: G11C7/1057 ,  G11C11/4074 ,  G11C5/147 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10

Abstract: A large-scale semiconductor integrated circuit comprising a low voltage-operated CMOS internal circuit, input and output circuits having bipolar transistors, said low voltage-operated CMOS internal circuit being supplied with an internal power supply voltage which is produced by dropping an external power supply voltage, and a level shifting circuit which converts the levels of signals in the chip. The input and output signals have the ECL level or the TTL level. The low voltage-operated CMOS internal circuit includes, for example, a DRAM of greater than 4 megabits and a microprocessor, and the internal operation voltage is smaller than 1.5 V. By the structure, a high-speed, low-power-consumption and low-noise semiconductor device is provided.

Abstract translation: 一种包括低压操作CMOS内部电路的大型半导体集成电路，具有双极型晶体管的输入和输出电路，所述低压操作的CMOS内部电路被提供内部电源电压，该内部电源电压通过将外部电源 电压和电平移位电路，其转换芯片中的信号电平。 输入和输出信号具有ECL电平或TTL电平。 低压操作的CMOS内部电路例如包括大于4兆比特的DRAM和微处理器，并且内部操作电压小于1.5V。通过该结构，高速，低功耗和 提供了低噪声半导体器件。

公开(公告)号：US4503522A

公开(公告)日：1985-03-05

申请号：US358678

申请日：1982-03-16

Applicant: Jun Etoh ,  Yoshiki Kawajiri ,  Ryoichi Hori ,  Kiyoo Itoh

Inventor： Jun Etoh ,  Yoshiki Kawajiri ,  Ryoichi Hori ,  Kiyoo Itoh

IPC: G11C11/408 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/40

CPC classification number: G11C11/4085 ,  G11C11/4096

Abstract: A dynamic type semiconductor memory using MOS transistors, in which first and second booster circuits utilizing capacitances, respectively, are provided at each of stages preceding and succeeding to a word driver, respectively. Data lines of the memory are each provided with a voltage compensating circuit for increasing a voltage for charging a memory cell to a level higher than a source voltage for being rewritten in the memory cell. A first boosting circuit is operated after a word line driving pulse signal is produced. Subsequently, word driver selecting transistors are turned off, which is followed by operation of the second booster circuit. Thus, the word line voltage is boosted twice.

Abstract translation: 使用MOS晶体管的动态型半导体存储器，其中分别在字驱动器之前和之后的每个级提供利用电容的第一和第二升压电路。 存储器的数据线各自设置有电压补偿电路，用于将用于将存储器单元充电的电压提高到高于用于在存储器单元中重写的源电压的电平。 在产生字线驱动脉冲信号之后，第一升压电路被操作。 随后，字驱动器选择晶体管截止，其后是第二升压电路的操作。 因此，字线电压被提升两次。

公开(公告)号：US4475181A

公开(公告)日：1984-10-02

申请号：US337099

申请日：1982-01-05

Applicant: Jun Etoh ,  Ryoichi Hori ,  Yoshiki Kawajiri ,  Kiyoo Itoh

Inventor： Jun Etoh ,  Ryoichi Hori ,  Yoshiki Kawajiri ,  Kiyoo Itoh

IPC: G11C8/00 ,  G11C8/06 ,  G11C8/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/418 ,  H03K5/135 ,  G11C7/00

CPC classification number: H03K5/135 ,  G11C11/407 ,  G11C11/408 ,  G11C11/418 ,  G11C8/06 ,  G11C8/18

Abstract: A semiconductor memory of multiplexed address inputs is made operative to receive column addresses and row addresses through common external address lines and to decode them consecutively in response to first and second strobe signals thereby to select one of memory cells. The semiconductor memory is equipped with address buffers exclusively for column and row addressing operations, respectively, the outputs of which are consecutively transmitted to column decoders and row decoders through common internal address lines.

Abstract translation: 多路复用地址输入的半导体存储器用于通过公共外部地址线接收列地址和行地址，并且响应于第一和第二选通信号连续解码它们，从而选择一个存储单元。 半导体存储器分别配备有用于列和行寻址操作的地址缓冲器，它们的输出通过公共内部地址线连续发送到列解码器和行解码器。

公开(公告)号：US08000137B2

公开(公告)日：2011-08-16

申请号：US12400015

申请日：2009-03-09

Applicant: Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

Inventor： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC: G11C16/04

CPC classification number: G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

Abstract: A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

Abstract translation: 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US07701778B2

公开(公告)日：2010-04-20

申请号：US11684035

申请日：2007-03-09

Applicant: Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

Inventor： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC: G11C11/34

CPC classification number: G11C16/3436

Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Abstract translation: 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20090244972A1

公开(公告)日：2009-10-01

申请号：US12400015

申请日：2009-03-09

Applicant: Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

Inventor： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC: G11C14/00 ,  G11C16/04 ,  G11C7/06

CPC classification number: G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

Abstract: A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

Abstract translation: 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US07512007B2

公开(公告)日：2009-03-31

申请号：US11971887

申请日：2008-01-09

Applicant: Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

Inventor： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C5/14

CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract translation: 从非易失性存储器的低功耗模式的释放到读取操作的重新开始的延迟降低。 可以电重写存储的信息的非易失性存储器在阱区中具有多个非易失性存储单元晶体管，其具有分别耦合到位线和源极线的漏电极和源电极以及耦合到字线的栅电极，并且基于阈值电压之间的差存储信息 读操作中的字线选择电平，而非易失性存储器具有低功耗模式。 在低功耗模式中，将低于电路接地电压并高于读操作所需的第一负电压的第二电压提供给阱区和字线。 当升压形成重写负电压时，负电压的电路节点不是低功耗模式下的电路接地电压。

公开(公告)号：US20080279011A1

公开(公告)日：2008-11-13

申请号：US12171724

申请日：2008-07-11

Applicant: YOSHIKI KAWAJIRI ,  Masaaki Terasawa ,  Takanori Yamazoe

Inventor： YOSHIKI KAWAJIRI ,  Masaaki Terasawa ,  Takanori Yamazoe

IPC: G11C16/04

CPC classification number: G11C5/145 ,  G11C16/12

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract translation: 本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。 在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。 在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为 选择时钟信号到电荷泵以将电压升高到预定的电压电平。 以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。