公开(公告)号：US07254084B2

公开(公告)日：2007-08-07

申请号：US11138344

申请日：2005-05-27

Applicant: Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

Inventor： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC: G11C5/14 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

公开(公告)号：US20080137429A1

公开(公告)日：2008-06-12

申请号：US11971887

申请日：2008-01-09

Applicant: Masaaki TERASAWA ,  Yoshiki Kawajiri ,  Takanori Yamazoe

Inventor： Masaaki TERASAWA ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC: G11C16/06

CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract translation: 从非易失性存储器的低功耗模式的释放到读取操作的重新开始的延迟降低。 可以电重写存储的信息的非易失性存储器在阱区中具有多个非易失性存储单元晶体管，其具有分别耦合到位线和源极线的漏电极和源电极以及耦合到字线的栅电极，并且基于阈值电压之间的差存储信息 读操作中的字线选择电平，而非易失性存储器具有低功耗模式。 在低功耗模式中，将低于电路接地电压并高于读操作所需的第一负电压的第二电压提供给阱区和字线。 当升压形成重写负电压时，负电压的电路节点不是低功耗模式下的电路接地电压。

公开(公告)号：US07652924B2

公开(公告)日：2010-01-26

申请号：US12171724

申请日：2008-07-11

Applicant: Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

Inventor： Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

IPC: G11C16/04

CPC classification number: G11C5/145 ,  G11C16/12

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract translation: 本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。 在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。 在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为 选择时钟信号到电荷泵以将电压升高到预定的电压电平。 以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。

公开(公告)号：US07512007B2

公开(公告)日：2009-03-31

申请号：US11971887

申请日：2008-01-09

Applicant: Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

Inventor： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C5/14

CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract translation: 从非易失性存储器的低功耗模式的释放到读取操作的重新开始的延迟降低。 可以电重写存储的信息的非易失性存储器在阱区中具有多个非易失性存储单元晶体管，其具有分别耦合到位线和源极线的漏电极和源电极以及耦合到字线的栅电极，并且基于阈值电压之间的差存储信息 读操作中的字线选择电平，而非易失性存储器具有低功耗模式。 在低功耗模式中，将低于电路接地电压并高于读操作所需的第一负电压的第二电压提供给阱区和字线。 当升压形成重写负电压时，负电压的电路节点不是低功耗模式下的电路接地电压。

公开(公告)号：US20080279011A1

公开(公告)日：2008-11-13

申请号：US12171724

申请日：2008-07-11

Applicant: YOSHIKI KAWAJIRI ,  Masaaki Terasawa ,  Takanori Yamazoe

Inventor： YOSHIKI KAWAJIRI ,  Masaaki Terasawa ,  Takanori Yamazoe

IPC: G11C16/04

CPC classification number: G11C5/145 ,  G11C16/12

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract translation: 本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。 在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。 在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为 选择时钟信号到电荷泵以将电压升高到预定的电压电平。 以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。

公开(公告)号：US07411831B2

公开(公告)日：2008-08-12

申请号：US11819288

申请日：2007-06-26

Applicant: Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

Inventor： Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

IPC: G11C16/04

CPC classification number: G11C5/145 ,  G11C16/12

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract translation: 本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。 在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。 在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为 选择时钟信号到电荷泵以将电压升高到预定的电压电平。 以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。

公开(公告)号：US07385853B2

公开(公告)日：2008-06-10

申请号：US11819974

申请日：2007-06-29

Applicant: Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

Inventor： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC: G11C11/34 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract translation: 从非易失性存储器的低功耗模式的释放到读取操作的重新开始的延迟降低。 可以电重写存储的信息的非易失性存储器在阱区中具有多个非易失性存储单元晶体管，其具有分别耦合到位线和源极线的漏电极和源电极以及耦合到字线的栅电极，并且基于阈值电压之间的差存储信息 读操作中的字线选择电平，而非易失性存储器具有低功耗模式。 在低功耗模式中，将低于电路接地电压并高于读操作所需的第一负电压的第二电压提供给阱区和字线。 当升压形成重写负电压时，负电压的电路节点不是低功耗模式下的电路接地电压。

公开(公告)号：US20070274129A1

公开(公告)日：2007-11-29

申请号：US11819974

申请日：2007-06-29

Applicant: Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

Inventor： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC: G11C11/34

CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract translation: 从非易失性存储器的低功耗模式的释放到读取操作的重新开始的延迟降低。 可以电重写存储的信息的非易失性存储器在阱区中具有多个非易失性存储单元晶体管，其具有分别耦合到位线和源极线的漏电极和源电极以及耦合到字线的栅电极，并且基于阈值电压之间的差存储信息 读操作中的字线选择电平，而非易失性存储器具有低功耗模式。 在低功耗模式中，将低于电路接地电压并高于读操作所需的第一负电压的第二电压提供给阱区和字线。 当升压形成重写负电压时，负电压的电路节点不是低功耗模式下的电路接地电压。

公开(公告)号：US20070247920A1

公开(公告)日：2007-10-25

申请号：US11819288

申请日：2007-06-26

Applicant: Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

Inventor： Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

IPC: G11C7/00

CPC classification number: G11C5/145 ,  G11C16/12

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract translation: 本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。 在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。 在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为 选择时钟信号到电荷泵以将电压升高到预定的电压电平。 以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。

公开(公告)号：US07251162B2

公开(公告)日：2007-07-31

申请号：US11115132

申请日：2005-04-27

Applicant: Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

Inventor： Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

IPC: G11C16/04

CPC classification number: G11C5/145 ,  G11C16/12

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract translation: 本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。 在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。 在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为 选择时钟信号到电荷泵以将电压升高到预定的电压电平。 以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。