公开(公告)号：US20060281249A1

公开(公告)日：2006-12-14

申请号：US11450903

申请日：2006-06-08

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/8242

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.

摘要翻译： 场效应晶体管如下形成。 提供了具有延伸在半导体区域上的具有第二导电性的外延层的第一导电类型的半导体区域。 形成延伸穿过外延层并终止在半导体区域中的沟槽。 执行第一导电类型的掺杂剂的双向成角度注入，从而沿着沟槽侧壁形成第一导电类型的区域。 执行阈值电压调整第二导电类型的掺杂剂的注入，从而将沿沟槽的上侧壁延伸的第一导电类型区域的一部分的导电类型转换为第二导电类型。 形成沟槽每一侧的第一导电类型的源区。

公开(公告)号：US07033891B2

公开(公告)日：2006-04-25

申请号：US10269126

申请日：2002-10-03

申请人： Peter H. Wilson ,  Steven Sapp ,  Neill Thornton

发明人： Peter H. Wilson ,  Steven Sapp ,  Neill Thornton

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7834 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

摘要： A MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices is described. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability.

摘要翻译： 描述了用于RF应用的MOSFET器件，其使用沟槽栅极代替横向MOSFET器件中使用的横向栅极。 本发明的器件中的沟槽栅被提供有用于高频增益的单个短通道。 本发明的器件还在沟槽栅极中提供不对称氧化物，以及降低栅极 - 漏极电容以提高RF性能的LDD区域。 这些特征允许这些器件保持LDMOS结构的优点（更好的线性度），从而增加RF功率增益。 本发明的沟槽栅极LDMOS还通过减少峰值电场和冲击电离而与常规LDMOS器件相比降低了热载流子效应。 因此，本发明的装置将具有更好的击穿能力。

公开(公告)号：US20050023607A1

公开(公告)日：2005-02-03

申请号：US10931887

申请日：2004-08-31

申请人： Steven Sapp ,  Peter Wilson

发明人： Steven Sapp ,  Peter Wilson

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/7802 ,  H01L29/7813

摘要： In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

摘要翻译： 根据本发明的实施例，MOSFET包括在第一半导体区域中横向间隔开的至少两个绝缘填充沟槽区域，以在其间形成漂移区域，以及至少一个电阻元件沿着每个 两个绝缘填充沟槽区域。 调整每个绝缘填充沟槽区域的宽度与漂移区域的宽度的比率，使得MOSFET的输出电容最小化。

公开(公告)号：US06828195B2

公开(公告)日：2004-12-07

申请号：US10347254

申请日：2003-01-17

申请人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Edward Probst

发明人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Edward Probst

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

摘要翻译： 提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂 很好地围着沉重的身体下面的沉重的身体。

公开(公告)号：US06803626B2

公开(公告)日：2004-10-12

申请号：US10200056

申请日：2002-07-18

申请人： Steven Sapp ,  Peter H. Wilson

发明人： Steven Sapp ,  Peter H. Wilson

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/7802 ,  H01L29/7813

摘要： In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

摘要翻译： 根据本发明的实施例，MOSFET包括在第一半导体区域中横向间隔开的至少两个绝缘填充沟槽区域，以在其间形成漂移区域，以及至少一个电阻元件沿着每个 两个绝缘填充沟槽区域。 调整每个绝缘填充沟槽区域的宽度与漂移区域的宽度的比率，使得MOSFET的输出电容最小化。

公开(公告)号：US06566749B1

公开(公告)日：2003-05-20

申请号：US10050428

申请日：2002-01-15

申请人： Rajeev Joshi ,  Steven Sapp

发明人： Rajeev Joshi ,  Steven Sapp

IPC分类号： H01L2310

CPC分类号： H01L24/85 ,  H01L23/04 ,  H01L23/3675 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.

摘要翻译： 公开了一种半导体管芯封装。 在一个实施例中，封装包括包括垂直功率晶体管的半导体管芯。 源极电极和栅极接触区域位于半导体管芯的第一表面。 漏极位于半导体管芯的第二表面。 基底构件靠近半导体管芯的第二表面，并且远离半导体管芯的第一表面，并且覆盖设置在半导体管芯的第一表面上。 盖子耦合到基座构件并且适于将跳动从半导体管芯移出。

公开(公告)号：US06429481B1

公开(公告)日：2002-08-06

申请号：US08970221

申请日：1997-11-14

申请人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Edward Probst

发明人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Edward Probst

IPC分类号： H01L2978

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

摘要翻译： 提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂 很好地围着沉重的身体下面的沉重的身体。

公开(公告)号：US6033489A

公开(公告)日：2000-03-07

申请号：US86654

申请日：1998-05-29

申请人： Bruce Douglas Marchant ,  Steven Sapp ,  Thomas Welch

发明人： Bruce Douglas Marchant ,  Steven Sapp ,  Thomas Welch

IPC分类号： H01L21/306 ,  H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L21/302

CPC分类号： H01L29/66712 ,  H01L21/30608 ,  H01L29/0657 ,  H01L29/7802 ,  Y10T428/12528

摘要： A semiconductor substrate is provided that exhibits very low substrate resistance while also providing structural integrity and robustness to resist breakage during manufacturing. The invention also provides methods of making these semiconductor substrates. The semiconductor substrate includes a planar surface and a recess extending below the planar surface. Preferred substrates include a plurality of recesses arranged in an array.

摘要翻译： 提供了一种半导体衬底，其表现出非常低的衬底电阻，同时还提供结构完整性和鲁棒性以在制造过程中抵抗断裂。 本发明还提供制造这些半导体衬底的方法。 半导体衬底包括平坦表面和在平坦表面下方延伸的凹部。 优选的基板包括排列成阵列的多个凹槽。

公开(公告)号：US08487371B2

公开(公告)日：2013-07-16

申请号：US13074921

申请日：2011-03-29

申请人： Daniel M. Kinzer ,  Steven Sapp ,  Chung-Lin Wu ,  Oseob Jeon ,  Bigildis Dosdos

发明人： Daniel M. Kinzer ,  Steven Sapp ,  Chung-Lin Wu ,  Oseob Jeon ,  Bigildis Dosdos

IPC分类号： H01L29/66 ,  H01L23/62 ,  H01L27/088 ,  H01L21/338

CPC分类号： H01L29/7827 ,  H01L24/13 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance RDS(on) include using a two-metal drain contact technique. The RDS(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.

摘要翻译： 具有晶体管的晶体管的晶体管的晶体管的一侧制造晶圆级芯片级封装（WLCSP）器件的系统和方法仍然具有优异的电气性能，低漏极 - 源极电阻RDS（on）包括使用 双金属漏极接触技术。 通过使用穿硅通孔（TSV）技术来形成漏极接触或通过使用紧密连接到漏极漂移的铜层来进一步改善RDS（on）。

公开(公告)号：US08329508B2

公开(公告)日：2012-12-11

申请号：US12823805

申请日：2010-06-25

申请人： Hamza Yilmaz ,  Steven Sapp ,  Qi Wang ,  Minhua Li ,  James J. Murphy ,  John Robert Diroll

发明人： Hamza Yilmaz ,  Steven Sapp ,  Qi Wang ,  Minhua Li ,  James J. Murphy ,  John Robert Diroll

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3114 ,  H01L23/481 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/072 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06102 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

摘要翻译： 公开了一种半导体管芯封装。 半导体管芯封装包括金属基板和半导体管芯，其包括第一表面，第一表面包括第一电端子，第二表面，包括第二电端子和至少一个孔。 金属基板附接到第二表面。 多个导电结构在半导体管芯上，并且包括设置在该至少一个孔中的至少一个导电结构。 其他导电结构可以设置在半导体管芯的第一表面上。