公开(公告)号：US08304829B2

公开(公告)日：2012-11-06

申请号：US12408552

申请日：2009-03-20

申请人： Joseph A. Yedinak ,  Ashok Challa

发明人： Joseph A. Yedinak ,  Ashok Challa

IPC分类号： H01L29/66

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

公开(公告)号：US20110303975A1

公开(公告)日：2011-12-15

申请号：US13152041

申请日：2011-06-02

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US20100308402A1

公开(公告)日：2010-12-09

申请号：US12480065

申请日：2009-06-08

申请人： Suku Kim ,  Dan Calafut ,  Ihsiu Ho ,  Dan Kinzer ,  Steven Sapp ,  Ashok Challa ,  Seokjin Jo ,  Mark Larsen

发明人： Suku Kim ,  Dan Calafut ,  Ihsiu Ho ,  Dan Kinzer ,  Steven Sapp ,  Ashok Challa ,  Seokjin Jo ,  Mark Larsen

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0865 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4933

摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

摘要翻译： 描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近 源区。 因此，在主线状沟槽内形成较小的支柱沟槽。 这种架构产生基本垂直于常规线形通道排列的附加通道区域。 常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。 通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。 描述其他实施例。

公开(公告)号：US20100140695A1

公开(公告)日：2010-06-10

申请号：US12408552

申请日：2009-03-20

申请人： Joseph A. Yedinak ,  Ashok Challa

发明人： Joseph A. Yedinak ,  Ashok Challa

IPC分类号： H01L29/78

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

公开(公告)号：US20100140689A1

公开(公告)日：2010-06-10

申请号：US12421448

申请日：2009-04-09

申请人： Joseph A. Yedinak ,  Ashok Challa ,  Daniel M. Kinzer ,  Dean E. Probst

发明人： Joseph A. Yedinak ,  Ashok Challa ,  Daniel M. Kinzer ,  Dean E. Probst

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

摘要翻译： 公开了具有提供增加的击穿电压和其它益处的特征的功率半导体器件。

公开(公告)号：US20080138953A1

公开(公告)日：2008-06-12

申请号：US12032599

申请日：2008-02-15

申请人： Ashok Challa ,  Alan Elbanhawy ,  Dean E. Probst ,  Steven P. Sapp ,  Peter H. Wilson ,  Babak S. Sani ,  Becky Losee ,  Robert Herrick ,  James J. Murphy ,  Gordon K. Madson ,  Bruce D. Marchant ,  Christopher B. Kocon ,  Debra S. Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Dean E. Probst ,  Steven P. Sapp ,  Peter H. Wilson ,  Babak S. Sani ,  Becky Losee ,  Robert Herrick ,  James J. Murphy ,  Gordon K. Madson ,  Bruce D. Marchant ,  Christopher B. Kocon ,  Debra S. Woolsey

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.

摘要翻译： 在半导体衬底中形成的沟槽的底部形成厚氧化物的方法包括形成填充沟槽并覆盖衬底的顶表面的共形氧化物膜。 并且将氧化膜从衬底的顶表面和沟槽内部蚀刻，以留下在沟槽底部具有目标厚度的基本平坦的氧化物层。 氧化膜可以通过亚大气压化学气相沉积工艺，定向四乙氧基硅油（TEOS）工艺或高密度等离子体沉积工艺进行沉积，其在沟槽底部形成比在沟槽的侧壁上更厚的氧化物。

公开(公告)号：US20060281249A1

公开(公告)日：2006-12-14

申请号：US11450903

申请日：2006-06-08

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/8242

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.

摘要翻译： 场效应晶体管如下形成。 提供了具有延伸在半导体区域上的具有第二导电性的外延层的第一导电类型的半导体区域。 形成延伸穿过外延层并终止在半导体区域中的沟槽。 执行第一导电类型的掺杂剂的双向成角度注入，从而沿着沟槽侧壁形成第一导电类型的区域。 执行阈值电压调整第二导电类型的掺杂剂的注入，从而将沿沟槽的上侧壁延伸的第一导电类型区域的一部分的导电类型转换为第二导电类型。 形成沟槽每一侧的第一导电类型的源区。

公开(公告)号：US06696726B1

公开(公告)日：2004-02-24

申请号：US09640955

申请日：2000-08-16

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368

摘要： A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.

摘要翻译： 垂直沟槽双扩散金属氧化物半导体（DMOS）场效应晶体管，其特征在于降低的漏极 - 源极电阻和较低的栅极电荷，并提供高跨导和增强的频率响应。

公开(公告)号：US08936985B2

公开(公告)日：2015-01-20

申请号：US13418128

申请日：2012-03-12

申请人： Ashok Challa ,  Alan Elbanhawy ,  Dean E. Probst ,  Steven P. Sapp ,  Peter H. Wilson ,  Babak S. Sani ,  Becky Losee ,  Robert Herrick ,  James J. Murphy ,  Gordon K. Madson ,  Bruce D. Marchant ,  Christopher B. Kocon ,  Debra S. Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Dean E. Probst ,  Steven P. Sapp ,  Peter H. Wilson ,  Babak S. Sani ,  Becky Losee ,  Robert Herrick ,  James J. Murphy ,  Gordon K. Madson ,  Bruce D. Marchant ,  Christopher B. Kocon ,  Debra S. Woolsey

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/683 ,  H01L21/311 ,  H01L29/40 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/739 ,  H02M3/335 ,  H02M3/00 ,  H01L29/10 ,  H02M7/48 ,  H01L29/49 ,  H01L29/423 ,  H01L29/165 ,  H01L23/495 ,  H01L21/265 ,  H01L29/417 ,  H01L23/498

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.

摘要翻译： 一种方法可以包括形成漂移区，在漂移区上形成阱区，以及形成延伸穿过阱区并进入漂移区的有源沟槽。 该方法可以包括形成与有源沟槽的第一侧壁接触的第一源极区域和与有源沟槽的第二侧壁接触的第二源极区域。 该方法还包括形成电荷控制沟槽，其中电荷控制沟槽平行于有源沟槽对齐并且通过台面区域与有源沟槽横向分离，并且其中阱区域的部分与电荷控制沟槽接触， 排除任何来源地区。 该方法还包括沿有源沟槽的底部沿着有源沟槽的第一侧壁形成厚度大于氧化物厚度的氧化物。

公开(公告)号：US08710584B2

公开(公告)日：2014-04-29

申请号：US13344269

申请日：2012-01-05

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate, the substrate being heavily doped and of a first conductivity type, a substrate cap region disposed on the substrate, the substrate cap region being heavily doped and of the first conductivity type and a body region disposed on the substrate cap region, the body region being lightly doped and of a second conductivity type. The MOSFET also includes a trench extending into the body region, a source region of the first conductivity type disposed in the body region and in contact with an upper portion of a sidewall of the trench and an out-diffusion region of the first conductivity type formed such that a spacing between the source region and the out-diffusion region defines a channel region of the MOSFET extending along the sidewall of the trench.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括衬底，衬底被重掺杂并具有第一导电类型，衬底帽区域设置在衬底上，衬底帽区域被重掺杂并且具有第一导电类型 以及设置在所述基板盖区域上的主体区域，所述主体区域被轻掺杂并具有第二导电类型。 MOSFET还包括延伸到体区的沟槽，设置在体区中并与沟槽的侧壁的上部接触的第一导电类型的源区和形成的第一导电类型的扩散区 使得源极区域和外扩散区域之间的间隔限定沿着沟槽的侧壁延伸的MOSFET的沟道区域。