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    Method of forming a dual-trench field effect transistor
    1.
    发明授权
    Method of forming a dual-trench field effect transistor 有权
    形成双沟道场效应晶体管的方法

    公开(公告)号：US08829641B2

    公开(公告)日：2014-09-09

    申请号：US12893997

    申请日：2010-09-29

    申请人： Bruce D. Marchant

    发明人： Bruce D. Marchant

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095

    摘要： In one general aspect, a method of forming a field effect transistor can include forming a well region in a semiconductor region of a first conductivity type where the well region is of a second conductivity type and has an upper surface and a lower surface. The method can include forming a gate trench extending into the semiconductor region to a depth below a depth of the lower surface of the well region, and forming a stripe trench extending through the well region and into the semiconductor region to a depth below the depth of the gate trench. The method can also include forming a contiguous source region of the first conductivity type in the well region where the source region being in contact with the gate trench and in contact with the stripe trench.

    摘要翻译： 在一个一般方面，形成场效应晶体管的方法可以包括在第一导电类型的半导体区域中形成阱区，其中阱区是第二导电类型并具有上表面和下表面。 该方法可以包括形成延伸到半导体区域中的深度低于阱区的下表面的深度的栅极沟槽，以及形成延伸穿过阱区并进入半导体区域的条状沟槽，深度低于 门沟。 该方法还可以包括在源极区域与栅极沟槽接触并与条状沟槽接触的阱区域中形成第一导电类型的连续源极区域。

    Lateral drain MOSFET with improved clamping voltage control
    2.
    发明授权
    Lateral drain MOSFET with improved clamping voltage control 有权
    具有改进的钳位电压控制的侧漏MOSFET

    公开(公告)号：US07998819B2

    公开(公告)日：2011-08-16

    申请号：US12849535

    申请日：2010-08-03

    申请人： Bruce D. Marchant ,  Dean Probst

    发明人： Bruce D. Marchant ,  Dean Probst

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7821 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66696

    摘要： A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.

    摘要翻译： 具有衬底的横向MOSFET，在衬底上生长的第一和第二外延层和形成在栅极电介质上的栅电极，栅极电介质又形成在第二外延层的顶表面上。 第二外延层包括漏极区域，其延伸到外延层的顶表面并且靠近栅电极的第一边缘，源区域延伸到第二外延层的顶表面并且接近第二外延层 栅电极的边缘，在源极区的至少一部分下方的重掺杂体，以及位于第一和第二外延层的过渡区附近的栅电介质下的轻掺杂阱。 重掺杂体之下的重掺杂体和第一外延区之间的PN结具有雪崩击穿电压，其基本上取决于在重掺杂体下面的第一外延层的上部的掺杂浓度。

    LATERAL DRAIN MOSFET WITH IMPROVED CLAMPING VOLTAGE CONTROL
    7.
    发明申请
    LATERAL DRAIN MOSFET WITH IMPROVED CLAMPING VOLTAGE CONTROL 有权

    公开(公告)号：US20100317168A1

    公开(公告)日：2010-12-16

    申请号：US12849535

    申请日：2010-08-03

    申请人： Bruce D. Marchant ,  Dean Probst

    发明人： Bruce D. Marchant ,  Dean Probst

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7821 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66696

    摘要： A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.

    Method of Forming Trench Gate FETs with Reduced Gate to Drain Charge
    8.
    发明申请
    Method of Forming Trench Gate FETs with Reduced Gate to Drain Charge 有权
    形成具有减小栅极的沟槽栅极FET以排放电荷的方法

    公开(公告)号：US20080166846A1

    公开(公告)日：2008-07-10

    申请号：US12052135

    申请日：2008-03-20

    申请人： Bruce D. Marchant ,  Ashok Challa

    发明人： Bruce D. Marchant ,  Ashok Challa

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66734

    摘要： A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches. A gate dielectric layer having a non-uniform thickness is formed along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is: (i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions. A gate electrode is formed in each trench.

    摘要翻译： 一种用于形成FET的方法包括以下步骤。 沟槽形成在第一导电类型的半导体区域中。 在半导体区域中形成第二导电类型的阱区域。 在阱区中形成第一导电类型的源极区，使得由阱区中的间隔和阱区的底表面限定的沟道区形成在沿着沟槽的相对侧壁的阱区中。 沿着沟槽的相对侧壁形成具有不均匀厚度的栅极电介质层，使得栅极电介质层沿着沟道区的至少下部的厚度变化为：（i）基本上线性，和（ ii）反向依赖于沟道区域下部的掺杂浓度的变化。 在每个沟槽中形成栅电极。

    Method of forming a field effect transistor having a lateral depletion structure
    9.
    发明授权
    Method of forming a field effect transistor having a lateral depletion structure 有权
    形成具有横向耗尽结构的场效应晶体管的方法

    公开(公告)号：US06818513B2

    公开(公告)日：2004-11-16

    申请号：US10741464

    申请日：2003-12-18

    申请人： Bruce D. Marchant

    发明人： Bruce D. Marchant

    IPC分类号： H01L21336

    CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095

    摘要： A method of forming a field effect transistor device includes: forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type, the semiconductor substrate having a major surface and a drain region; forming a source region of the first conductivity type in the well region; forming a trench gate electrode adjacent to the source region; forming a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth; and depositing a semiconductor material of the second conductivity type within the stripe trench.

    摘要翻译： 形成场效应晶体管器件的方法包括：在第一导电类型的半导体衬底中形成具有第二导电类型的阱区，所述半导体衬底具有主表面和漏极区; 在所述阱区中形成所述第一导电类型的源区; 形成邻近所述源极区的沟槽栅电极; 形成从半导体衬底的主表面延伸到半导体衬底到预定深度的条状沟槽; 以及在条形沟槽内沉积第二导电类型的半导体材料。