公开(公告)号：US20120119291A1

公开(公告)日：2012-05-17

申请号：US13270050

申请日：2011-10-10

申请人： Robert Herrick ,  Becky Losee ,  Dean Probst

发明人： Robert Herrick ,  Becky Losee ,  Dean Probst

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/7802 ,  Y10S257/905

摘要： A field effect transistor (FET) includes a plurality of trenches extending into a silicon layer, each trench having upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches. Source regions that are self-aligned to corresponding trenches extend in the body regions adjacent opposing sidewalls of each trench, and have a conductivity type opposite that of the body regions.

摘要翻译： 场效应晶体管（FET）包括延伸到硅层的多个沟槽，每个沟槽具有扇出的上侧壁。 接触开口延伸到相邻沟槽之间的硅层中，使得每个沟槽和相邻的接触开口形成共同的上侧壁部分。 主体区域在相邻沟槽之间延伸。 与对应的沟槽自对准的源极区域在与每个沟槽的相对侧壁相邻的主体区域中延伸，并且具有与身体区域相反的导电类型。

公开(公告)号：US07595524B2

公开(公告)日：2009-09-29

申请号：US12049996

申请日：2008-03-17

申请人： Robert Herrick ,  Becky Losee ,  Dean Probst

发明人： Robert Herrick ,  Becky Losee ,  Dean Probst

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/7802 ,  Y10S257/905

摘要： A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches, and source regions extend in the body regions adjacent opposing sidewalls of each trench. The source regions have a conductivity type opposite that of the body regions.

摘要翻译： 场效应晶体管包括延伸到硅层的多个沟槽。 每个沟槽具有扇出的上侧壁。 接触开口延伸到相邻沟槽之间的硅层中，使得每个沟槽和相邻的接触开口形成共同的上侧壁部分。 主体区域在相邻沟槽之间延伸，并且源区域在与每个沟槽的相对侧壁相邻的主体区域中延伸。 源区具有与体区相反的导电性。

公开(公告)号：US20060214222A1

公开(公告)日：2006-09-28

申请号：US11445111

申请日：2006-05-31

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J. Jung ,  H. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J. Jung ,  H. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

公开(公告)号：US08680611B2

公开(公告)日：2014-03-25

申请号：US13600184

申请日：2012-08-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L29/76

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

摘要翻译： 根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。 该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。 源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。 该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。 导体层可与半导体区形成肖特基接触。

公开(公告)号：US20120319197A1

公开(公告)日：2012-12-20

申请号：US13600184

申请日：2012-08-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

摘要翻译： 根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。 该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。 源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。 该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。 导体层可与半导体区形成肖特基接触。

公开(公告)号：US07998819B2

公开(公告)日：2011-08-16

申请号：US12849535

申请日：2010-08-03

申请人： Bruce D. Marchant ,  Dean Probst

发明人： Bruce D. Marchant ,  Dean Probst

IPC分类号： H01L21/336

CPC分类号： H01L29/7821 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66696

摘要： A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.

摘要翻译： 具有衬底的横向MOSFET，在衬底上生长的第一和第二外延层和形成在栅极电介质上的栅电极，栅极电介质又形成在第二外延层的顶表面上。 第二外延层包括漏极区域，其延伸到外延层的顶表面并且靠近栅电极的第一边缘，源区域延伸到第二外延层的顶表面并且接近第二外延层 栅电极的边缘，在源极区的至少一部分下方的重掺杂体，以及位于第一和第二外延层的过渡区附近的栅电介质下的轻掺杂阱。 重掺杂体之下的重掺杂体和第一外延区之间的PN结具有雪崩击穿电压，其基本上取决于在重掺杂体下面的第一外延层的上部的掺杂浓度。

公开(公告)号：US07598144B2

公开(公告)日：2009-10-06

申请号：US11952481

申请日：2007-12-07

申请人： Robert Herrick ,  Dean Probst ,  Fred Session

发明人： Robert Herrick ,  Dean Probst ,  Fred Session

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734

摘要： A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.

摘要翻译： 形成屏蔽栅沟槽FET的方法包括以下步骤。 在第一导电类型的硅区域中形成沟槽。 屏蔽电极形成在沟槽的底部。 沿着屏蔽电极的上表面形成包括热氧化物层和保形电介质层的多晶硅电介质（IPD）。 形成至少上沟槽侧壁的栅电介质衬里。 在沟槽中形成栅电极，使得栅电极通过IPD与屏蔽电极绝缘。

公开(公告)号：US20080090339A1

公开(公告)日：2008-04-17

申请号：US11952481

申请日：2007-12-07

申请人： Robert Herrick ,  Dean Probst ,  Fred Session

发明人： Robert Herrick ,  Dean Probst ,  Fred Session

IPC分类号： H01L21/00

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734

摘要： A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.

摘要翻译： 形成屏蔽栅沟槽FET的方法包括以下步骤。 在第一导电类型的硅区域中形成沟槽。 屏蔽电极形成在沟槽的底部。 沿着屏蔽电极的上表面形成包括热氧化物层和保形电介质层的多晶硅电介质（IPD）。 形成至少上沟槽侧壁的栅电介质衬里。 在沟槽中形成栅电极，使得栅电极通过IPD与屏蔽电极绝缘。

公开(公告)号：US07078296B2

公开(公告)日：2006-07-18

申请号：US10052234

申请日：2002-01-16

申请人： Duc Chau ,  Becky Losee ,  Bruce Marchant ,  Dean Probst ,  Robert Herrick ,  James Murphy

发明人： Duc Chau ,  Becky Losee ,  Bruce Marchant ,  Dean Probst ,  Robert Herrick ,  James Murphy

IPC分类号： H01L21/8232

CPC分类号： H01L27/088 ,  H01L21/823487

摘要： Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOSFET is provided by making the sidewall of the overlying isolation dielectric layer substantially aligned with the sidewall of the gate conductor. Such an alignment can be made through any number of methods such as using a dual dielectric process, using a selective dielectric oxidation process, using a selective dielectric deposition process, or a spin-on-glass dielectric process.

摘要翻译： 公开了自对准沟槽MOSFET及其制造方法。 通过具有自对准结构，每单位面积的MOSFET的数量（单元密度）增加，使得MOSFET更便宜地生产。 MOSFET的自对准结构通过使覆盖隔离电介质层的侧壁基本上与栅极导体的侧壁对准来提供。 这种对准可以通过任何数量的方法进行，例如使用双电介质方法，使用选择性介电氧化工艺，使用选择性电介质沉积工艺或旋涂玻璃介电工艺。

公开(公告)号：US20050191794A1

公开(公告)日：2005-09-01

申请号：US11111305

申请日：2005-04-20

申请人： Robert Herrick ,  Becky Losee ,  Dean Probst

发明人： Robert Herrick ,  Becky Losee ,  Dean Probst

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L21/332 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/7802 ,  Y10S257/905

摘要： A semiconductor device is formed as follows. A plurality of trenches is formed in a silicon layer. An insulating layer filling an upper portion of each trench is formed. Exposed silicon is removed from adjacent the trenches to expose an edge of the insulating layer in each trench, such that the exposed edge of the insulating layer in each trench defines a portion of each contact opening formed between every two adjacent trenches.

摘要翻译： 如下形成半导体器件。 在硅层中形成多个沟槽。 形成填充每个沟槽的上部的绝缘层。 从相邻的沟槽去除暴露的硅以暴露每个沟槽中的绝缘层的边缘，使得每个沟槽中的绝缘层的暴露边缘限定形成在每两个相邻沟槽之间的每个接触开口的一部分。