公开(公告)号：US20070059874A1

公开(公告)日：2007-03-15

申请号：US11456054

申请日：2006-07-06

Applicant: Naim Moumen ,  Husam Alshareef ,  Joel Barnett ,  Muhammad Hussain ,  Hongfa Luan ,  Seung-Chul Song ,  Raj Jammy

Inventor： Naim Moumen ,  Husam Alshareef ,  Joel Barnett ,  Muhammad Hussain ,  Hongfa Luan ,  Seung-Chul Song ,  Raj Jammy

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned over an active region, exposing a portion of the common layer. A first ion may be deposited in the common layer forming a first mask layer. Similarly, a second mask layer may be deposited and patterned over the other active region and the first metal layer, and another portion of the common layer is exposed. A second ion may be deposited in the common layer, forming a second mask layer.

Abstract translation: 提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。 诸如金属层，金属合金层或金属氮化物层的公共层可以沉积到栅极电介质上。 可以在有源区上沉积和图案化第一掩模层，暴露公共层的一部分。 可以在形成第一掩模层的公共层中沉积第一离子。 类似地，第二掩模层可以在另一个有源区和第一金属层上沉积和图案化，并且公共层的另一部分被暴露。 可以在公共层中沉积第二离子，形成第二掩模层。

公开(公告)号：US20060227811A1

公开(公告)日：2006-10-12

申请号：US11218727

申请日：2005-09-02

Applicant: Muhammad Hussain ,  Imran Badr ,  Faisal Masood ,  Philip Dickinson ,  Richard Kessler ,  Daniel Katz ,  Michael Bertone ,  Robert Sanzone ,  Thomas Hummel ,  Gregg Bouchard

Inventor： Muhammad Hussain ,  Imran Badr ,  Faisal Masood ,  Philip Dickinson ,  Richard Kessler ,  Daniel Katz ,  Michael Bertone ,  Robert Sanzone ,  Thomas Hummel ,  Gregg Bouchard

IPC: H04J3/06

CPC classification number: H04L69/16 ,  H04L49/90 ,  H04L49/9047 ,  H04L69/163

Abstract: A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.

公开(公告)号：US20060075206A1

公开(公告)日：2006-04-06

申请号：US11220899

申请日：2005-09-07

Applicant: Gregg Bouchard ,  David Carlson ,  Richard Kessler ,  Muhammad Hussain

Inventor： Gregg Bouchard ,  David Carlson ,  Richard Kessler ,  Muhammad Hussain

IPC: G06F12/10

CPC classification number: G06F9/30003 ,  H04L1/0045

Abstract: A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of the fields includes an output reference for storing results generated responsive to the processed input data. The instructions are forwarded to a DFA engine adapted to process the input data using the identified DFA graph and to provide results as instructed by the output reference.

Abstract translation: 描述了一种用于遍历确定性有限自动机（DFA）图的计算机可读指令，以便在即将进行的分组数据中实时地执行模式搜索。 该指令包括一个或多个预定义字段。 其中一个字段包括用于标识几个先前存储的DFA图形之一的DFA图形标识符。 另一个领域包括用于使用所识别的DFA图形来识别要处理的输入数据的输入参考。 另一个领域包括用于存储响应于经处理的输入数据生成的结果的输出参考。 这些指令被转发到适用于使用识别的DFA图处理输入数据的DFA引擎，并根据输出参考的指示提供结果。

公开(公告)号：US20050060558A1

公开(公告)日：2005-03-17

申请号：US10411944

申请日：2003-04-12

Applicant: Muhammad Hussain ,  Philip Dickinson ,  Imran Badr

Inventor： Muhammad Hussain ,  Philip Dickinson ,  Imran Badr

IPC: G06F9/50 ,  H04L9/00 ,  G06F12/14

CPC classification number: G06F9/5088 ,  G06F9/5044 ,  H04L9/06 ,  H04L2209/125

Abstract: An apparatus is described comprising: a plurality of security processing resources for processing two or more different types of data traffic within a cryptographic processor; a first scheduler to provide a first type of data traffic to a first predefined subset of the security processing resources using a first scheduling technique; and a second scheduler to provide a second type of data traffic to a second predefined subset of the security processing resources using a second scheduling technique.

Abstract translation: 描述了一种装置，包括：用于在密码处理器内处理两个或多个不同类型的数据业务的多个安全处理资源; 第一调度器，使用第一调度技术向所述安全处理资源的第一预定义子集提供第一类型的数据业务; 以及第二调度器，使用第二调度技术向所述安全处理资源的第二预定义子集提供第二类型的数据业务。

公开(公告)号：USD811661S1

公开(公告)日：2018-02-27

申请号：US29564625

申请日：2016-05-13

Applicant: Muhammad Hussain ,  Farah Hussain

Designer： Muhammad Hussain ,  Farah Hussain

公开(公告)号：US20110006378A1

公开(公告)日：2011-01-13

申请号：US12498775

申请日：2009-07-07

Applicant: Muhammad Hussain ,  Chang Seo Park

Inventor： Muhammad Hussain ,  Chang Seo Park

IPC: H01L29/78 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/31111 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method of manufacturing a semiconductor device includes depositing a first capping layer on a dielectric layer. The method also includes etching the first capping layer from a second portion of the semiconductor device. The first capping layer remaining in a first portion of the semiconductor device may form a PMOS device. The method further includes depositing a second capping layer after etching the first capping layer. After the second capping layer is deposited a maskless process results in selectively etching the second capping layer from the first portion of the semiconductor device. The second portion of the semiconductor device may be a NMOS device. The method described may be used in manufacturing integrated CMOS devices as scaling reduces device size. Additionally, the method of selectively etching capping layers may be used to manufacture multi-threshold voltage devices.

Abstract translation: 制造半导体器件的方法包括在电介质层上沉积第一覆盖层。 该方法还包括从半导体器件的第二部分蚀刻第一覆盖层。 保留在半导体器件的第一部分中的第一覆盖层可以形成PMOS器件。 该方法还包括在蚀刻第一覆盖层之后沉积第二覆盖层。 在沉积第二覆盖层之后，无掩模工艺导致从半导体器件的第一部分选择性地蚀刻第二覆盖层。 半导体器件的第二部分可以是NMOS器件。 所描述的方法可以用于制造集成CMOS器件，因为缩放减小器件尺寸。 此外，选择性蚀刻封盖层的方法可用于制造多阈值电压器件。

公开(公告)号：US20070150347A1

公开(公告)日：2007-06-28

申请号：US11391088

申请日：2006-03-28

Applicant: Venkata Bhamidipati ,  Muhammad Hussain ,  Aftab Zia ,  M. Khan ,  John Kannapell ,  David Sobotka

Inventor： Venkata Bhamidipati ,  Muhammad Hussain ,  Aftab Zia ,  M. Khan ,  John Kannapell ,  David Sobotka

IPC: G06Q30/00

CPC classification number: G06Q30/02 ,  G06Q30/0256 ,  G06Q30/0257 ,  G06Q30/0269 ,  G06Q30/0273 ,  H04L67/20

Abstract: Systems and methods are provided for dynamically backfilling a deficient number of advertisements from an advertisement supplier. In one embodiment, a method includes identifying a first request from an advertisement requester, the first request identifying a desired number of advertisements to receive from a first advertisement supplier; identifying a first fetching period; sending the first request to the first advertisement supplier; monitoring to determine whether the desired number of advertisements from the first advertisement supplier are received within the first fetching period; and if the desired number of advertisements are not received within the first fetching period, performing a backfill mechanism to supply the desired number of advertisements.

Abstract translation: 提供了用于从广告供应商动态地回填缺少数量的广告的系统和方法。 在一个实施例中，一种方法包括从广告请求者识别第一请求，第一请求标识要从第一广告提供者接收的期望数量的广告; 识别第一个获取周期; 向第一广告供应商发送第一请求; 监视以确定在所述第一提取周期内是否接收到来自所述第一广告提供者的期望数量的广告; 并且如果在第一提取周期内没有接收到期望数量的广告，则执行回填机制以提供期望数量的广告。

公开(公告)号：US20060212936A1

公开(公告)日：2006-09-21

申请号：US11082068

申请日：2005-03-16

Applicant: Audrius Berzanskis ,  Harri Hakkarainen ,  Keun Lee ,  Muhammad Hussain

Inventor： Audrius Berzanskis ,  Harri Hakkarainen ,  Keun Lee ,  Muhammad Hussain

IPC: G06F15/16

CPC classification number: H04L63/061 ,  H04L9/0852 ,  H04L63/164

Abstract: A method of integrating quantum key distribution (QKD) with Internet protocol security (IPSec) to improve the security of IPSec. Standard IPSec protocols impose limits on the frequency at which keys can be changed. This makes efforts to improve the security of IPSec by employing quantum keys problematic. The method includes increasing the size of the Security Association (SA) Table in a manner that enables a high key change rate so that the quantum keys can be combined with the classical keys generated by Internet Key Exchange (IKE). The invention includes a method of creating the SA Table by combining quantum keys generated by the QKD process with classical keys generated by the IKE process, thereby enabling QKD-based IPSec.

Abstract translation: 将量子密钥分发（QKD）与互联网协议安全（IPSec）进行整合，提高IPSec的安全性。 标准IPSec协议对可以更改密钥的频率施加限制。 这使得通过使用量子钥匙来提高IPSec的安全性。 该方法包括以能够实现高密钥变化率的方式增加安全关联（SA）表的大小，使得量子密钥可以与因特网密钥交换（IKE）生成的经典密钥组合。 本发明包括一种通过将由QKD处理产生的量子密钥与IKE过程产生的经典密钥相结合来创建SA表的方法，由此实现基于QKD的IPSec。

公开(公告)号：US20060059286A1

公开(公告)日：2006-03-16

申请号：US11042476

申请日：2005-01-25

Applicant: Michael Bertone ,  David Carlson ,  Richard Kessler ,  Philip Dickinson ,  Muhammad Hussain ,  Trent Parker

Inventor： Michael Bertone ,  David Carlson ,  Richard Kessler ,  Philip Dickinson ,  Muhammad Hussain ,  Trent Parker

IPC: G06F13/24

CPC classification number: G06F12/084 ,  G06F9/30014 ,  G06F9/30043 ,  G06F9/30138 ,  G06F9/3824 ,  G06F9/383 ,  G06F11/3632 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0835 ,  G06F12/0875 ,  G06F12/0891 ,  G06F13/24 ,  G06F2212/6012 ,  G06F2212/6022

Abstract: In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every clock cycle to minimize delay between a triggering event and its respective interrupt signal. Each of the multiple processors also senses, or samples the global signal interconnect, preferably during the same cycle within which the pulse was provided, to determine the existence of an interrupt signal. Upon sensing an interrupt signal, each of the multiple processors responds to it substantially simultaneously. For example, an interrupt signal sampled by each of the multiple processors causes each processor to invoke a debug handler routine.

Abstract translation: 在多核处理器中，高速中断信号互连允许多个处理器在同一时间被中断。 例如，全局信号互连耦合到多个处理器中的每一个，每个处理器被配置为选择性地提供中断信号或其上的脉冲。 优选地，每个处理器内核能够在每个时钟周期期间脉冲全局信号互连以最小化触发事件与其各自的中断信号之间的延迟。 多个处理器中的每一个还优选地在提供脉冲的相同周期内感测或采样全局信号互连，以确定中断信号的存在。 在感测到中断信号时，多个处理器中的每一个基本上同时响应。 例如，由多个处理器中的每一个采样的中断信号使每个处理器调用调试处理程序。