公开(公告)号：US20100122146A1

公开(公告)日：2010-05-13

申请号：US12267017

申请日：2008-11-07

申请人： Hagop Nazarian ,  Ping Hou

发明人： Hagop Nazarian ,  Ping Hou

IPC分类号： G11C29/52 ,  G06F11/00

CPC分类号： G06F11/1072 ,  G11C2029/0411

摘要： Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

摘要翻译： 本文描述了提供电子存储器的单位和多位纠错。 作为示例，可以通过在一组分析的存储器单元的位级分布之间建立可疑区域来实现纠错。 可疑区域可以定义分布的潜在错误位。 如果对于分布检测到位错误，则可以首先将错误校正应用于可疑区域中的潜在错误位。 通过识别怀疑的错误位并将初始误差修正限制在这种识别的位上，可以减轻或避免对分布的所有位应用纠错所涉及的复杂性，从而提高电子存储器误码校正的效率。

公开(公告)号：US07602639B2

公开(公告)日：2009-10-13

申请号：US11957309

申请日：2007-12-14

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26

摘要： Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated.

摘要翻译： 这里描述了一个或多个多单元存储器件的重叠状态分布之间的区别。 作为示例，系统可以包括计算组件，其可以对所识别的非重叠位分布和与存储器单元相关联的重叠位分布执行数学运算。 这种数学运算可以产生结果分布，其可以促进由分析组件识别与一个或多个多单元存储器设备的单元相关联的至少一个重叠位分配。 因此，可以减轻与存储器单元装置的重叠位相关联的读取错误。

公开(公告)号：US20070247910A1

公开(公告)日：2007-10-25

申请号：US11407856

申请日：2006-04-20

申请人： Hagop Nazarian ,  Frankie Roohparvar

发明人： Hagop Nazarian ,  Frankie Roohparvar

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure, the string subdivided by a plurality of separator elements placed in series with the memory cells of the string, allowing for smaller erase blocks while maintaining the size of the string. The separator elements can be pass transistors or non-volatile or flash memory cells.

摘要翻译： NAND架构包括被分成较小子串进行擦除的大NAND串，该字符串被与字符串的存储单元串联放置的多个分隔元件细分，允许更小的擦除块，同时保持 串。 分离器元件可以是通过晶体管或非易失性或闪存单元。

公开(公告)号：US20060262602A1

公开(公告)日：2006-11-23

申请号：US11495245

申请日：2006-07-28

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30

摘要： NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel rds resistance and decreased “narrow width” effect, allowing for increased scaling of NAND memory cell strings. In addition, the required voltages for reading and programming operations are reduced, allowing the use of more efficient, lower voltage charge pumps and a reduction circuit element feature sizes and layouts. Cell inhibit of unselected cells is also increased, reducing the likelihood of cell disturb in the memory array. Operation speed is improved by increasing read current of the selected NAND string and by increasing the ability to overcome the RC time constants of circuit lines and capacitances through lowered voltage swings and increased current supplies.

摘要翻译： NAND架构描述了利用连续的信道增强和耗尽型浮动栅极存储器单元的闪存串，存储器阵列和存储器件。 耗尽模式浮栅存储器单元允许通过较低通道r ds电阻增加的单元电流和减小的“窄宽度”效应，从而允许增加NAND存储器单元串的缩放。 此外，读取和编程操作所需的电压降低，允许使用更有效，更低电压的电荷泵和降低电路元件特征尺寸和布局。 未选择的细胞的细胞抑制也增加，降低了存储器阵列中细胞干扰的可能性。 通过增加所选NAND串的读取电流并通过降低的电压摆幅和增加的电流供应来提高克服电路线和电容的RC时间常数的能力来提高操作速度。

公开(公告)号：US20060245272A1

公开(公告)日：2006-11-02

申请号：US11116842

申请日：2005-04-28

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

IPC分类号： G11C7/06

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

公开(公告)号：US20060245257A1

公开(公告)日：2006-11-02

申请号：US11454737

申请日：2006-06-16

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3427 ,  G11C2211/5648

摘要： The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The remaining cells on the wordline are programmed to their respective logical states in order of decreasing threshold voltage levels.

公开(公告)号：US20060238955A1

公开(公告)日：2006-10-26

申请号：US11475821

申请日：2006-06-27

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G01P1/10

CPC分类号： H03K19/017581 ,  G06J1/00

摘要： An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are, configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells.

摘要翻译： 混合模式集成电路系统的模拟部分包括多个模拟输入单元，多个模拟输出单元和互连阵列。 输入单元被配置为编程模拟功能。 输出单元被配置为提供与编程的模拟功能相对应的模拟和数字输出。 互连阵列将编程的模拟功能处理成指示模拟功能的信号。 互连阵列选择性地将信号提供给多个模拟输出单元。

公开(公告)号：US20060126378A1

公开(公告)日：2006-06-15

申请号：US11314722

申请日：2005-12-22

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C2213/78 ,  G11C2213/79

摘要： A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells associated with an addressed cell to a known number having a sneak path resistance that can be calculated and taken into consideration when sensing the addressed memory cell. Blocks of memory cells are associated with access transistors, which separate the memory cells connected thereto into one half (½) sections of cell blocks. The access transistors can be associated with n memory cells, where n is an even number of at least 2; there may or may not be an equal number of cells on either side of the transistor. The memory array has memory cells, which are grouped into 1T-2nCell blocks.

公开(公告)号：US5986489A

公开(公告)日：1999-11-16

申请号：US627946

申请日：1996-04-03

申请人： S. Babar Raza ,  Lin-Shih Liu ,  Hagop Nazarian

发明人： S. Babar Raza ,  Lin-Shih Liu ,  Hagop Nazarian

IPC分类号： H03K19/003 ,  H03K5/12

CPC分类号： H03K19/00361

摘要： A slew rate control circuit to control output slew rate according to a programmable reference signal. A slew rate control circuit limits the slew rate of a plurality output buffers according to a signal received from a programmable slew rate control reference.

摘要翻译： 一种转换速率控制电路，用于根据可编程参考信号来控制输出转换速率。 压摆率控制电路根据从可编程转换速率控制基准接收到的信号来限制多个输出缓冲器的转换速率。

公开(公告)号：US5821794A

公开(公告)日：1998-10-13

申请号：US626043

申请日：1996-04-01

申请人： Hagop Nazarian ,  Donald A. Krall ,  S. Babar Raza

发明人： Hagop Nazarian ,  Donald A. Krall ,  S. Babar Raza

IPC分类号： H03K19/177 ,  H03K1/04

CPC分类号： H03K19/1774

摘要： The present invention provides a clocking circuit allowing individual macrocells in a particular macrocell block of a CPLD to use different polarities of the same clock. The input clock pin can now drive all the macrocells directly, which can eliminate additional buffering states and improve the clock to out timing, Tco, by (for example) 300 ps. The clocks are presented directly to the clock selection multiplexers for each macrocell. Additional functioning may be realized by implementing additional configuration bits inside the clocking architecture.

摘要翻译： 本发明提供了一种时钟电路，其允许CPLD的特定宏小区块中的各个宏小区使用相同时钟的不同极性。 输入时钟引脚现在可以直接驱动所有宏单元，这可以消除额外的缓冲状态，并通过（例如）300 ps将时钟转换为时序Tco。 时钟直接显示给每个宏单元的时钟选择多路复用器。 额外的功能可以通过在时钟架构内实现附加配置位来实现。