公开(公告)号：US5986489A

公开(公告)日：1999-11-16

申请号：US627946

申请日：1996-04-03

申请人： S. Babar Raza ,  Lin-Shih Liu ,  Hagop Nazarian

发明人： S. Babar Raza ,  Lin-Shih Liu ,  Hagop Nazarian

IPC分类号： H03K19/003 ,  H03K5/12

CPC分类号： H03K19/00361

摘要： A slew rate control circuit to control output slew rate according to a programmable reference signal. A slew rate control circuit limits the slew rate of a plurality output buffers according to a signal received from a programmable slew rate control reference.

摘要翻译： 一种转换速率控制电路，用于根据可编程参考信号来控制输出转换速率。 压摆率控制电路根据从可编程转换速率控制基准接收到的信号来限制多个输出缓冲器的转换速率。

公开(公告)号：US5502403A

公开(公告)日：1996-03-26

申请号：US360469

申请日：1994-12-20

申请人： Lin-Shih Liu ,  Syed B. Raza ,  Hagop Nazarian ,  George M. Ansel ,  Stephen M. Douglass ,  Jeffery S. Hunt

发明人： Lin-Shih Liu ,  Syed B. Raza ,  Hagop Nazarian ,  George M. Ansel ,  Stephen M. Douglass ,  Jeffery S. Hunt

IPC分类号： H03K19/173 ,  H03K19/0948

CPC分类号： H03K19/1736

摘要： A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

摘要翻译： 用户可配置电路包含时钟逻辑，开关元件和数据路径电路。 在开关元件中接收输入数据，并且开关元件和数据路径电路构成电路的整个数据路径。 接收多个用户可配置输入以为特定用户应用配置电路。 时钟逻辑和开关元件实现可由用户可配置输入配置的逻辑功能。 逻辑功能在时钟逻辑中被预处理，从而在数据通路中发生最小的延迟。 此外，通过开关元件和寄存器的传播延迟与用户可配置输入无关。 本发明的用户可配置电路具有用作可编程逻辑器件的宏小区的应用，允许用户将电路配置为D型触发器，T型触发器。 此外，用户选择输出电路的极性。

公开(公告)号：US5621338A

公开(公告)日：1997-04-15

申请号：US584105

申请日：1996-01-11

申请人： Lin-Shih Liu ,  Syed B. Raza ,  Hagop Nazarian ,  George M. Ansel ,  Stephen M. Douglass ,  Jeffery S. Hunt

发明人： Lin-Shih Liu ,  Syed B. Raza ,  Hagop Nazarian ,  George M. Ansel ,  Stephen M. Douglass ,  Jeffery S. Hunt

IPC分类号： H03K19/173 ,  H03K19/0948

CPC分类号： H03K19/1736

摘要： A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

摘要翻译： 用户可配置电路包含时钟逻辑，开关元件和数据路径电路。 在开关元件中接收输入数据，并且开关元件和数据路径电路构成电路的整个数据路径。 接收多个用户可配置输入以为特定用户应用配置电路。 时钟逻辑和开关元件实现可由用户可配置输入配置的逻辑功能。 逻辑功能在时钟逻辑中被预处理，从而在数据通路中发生最小的延迟。 此外，通过开关元件和寄存器的传播延迟与用户可配置输入无关。 本发明的用户可配置电路具有用作可编程逻辑器件的宏小区的应用，允许用户将电路配置为D型触发器，T型触发器。 此外，用户选择输出电路的极性。

公开(公告)号：USRE37577E1

公开(公告)日：2002-03-12

申请号：US09047314

申请日：1998-03-24

申请人： Lin-Shih Liu ,  Syed Babar Raza ,  Hagop Nazarian ,  George M. Ansel ,  Stephen M. Douglass ,  Jeffrey Scott Hunt

发明人： Lin-Shih Liu ,  Syed Babar Raza ,  Hagop Nazarian ,  George M. Ansel ,  Stephen M. Douglass ,  Jeffrey Scott Hunt

IPC分类号： H03K19173

CPC分类号： H03K19/1736

摘要： A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

摘要翻译： 用户可配置电路包含时钟逻辑，开关元件和数据路径电路。 在开关元件中接收输入数据，并且开关元件和数据路径电路构成电路的整个数据路径。 接收多个用户可配置输入以为特定用户应用配置电路。 时钟逻辑和开关元件实现可由用户可配置输入配置的逻辑功能。 逻辑功能在时钟逻辑中被预处理，从而在数据通路中发生最小的延迟。 此外，通过开关元件和寄存器的传播延迟与用户可配置输入无关。 本发明的用户可配置电路具有用作可编程逻辑器件的宏小区的应用，允许用户将电路配置为D型触发器，T型触发器。 此外，用户选择输出电路的极性。

公开(公告)号：US07995375B2

公开(公告)日：2011-08-09

申请号：US12169598

申请日：2008-07-08

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC分类号： G11C11/00

CPC分类号： G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

摘要： Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

摘要翻译： 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US07385423B1

公开(公告)日：2008-06-10

申请号：US11114827

申请日：2005-04-26

申请人： Lin-Shih Liu ,  Mark T Chan

发明人： Lin-Shih Liu ,  Mark T Chan

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/01721

摘要： A low-power low-voltage buffer with a half-latch is provided. The half-latch buffer design may provide increased speed without dramatically increasing power consumption.

摘要翻译： 提供具有半锁存器的低功率低电压缓冲器。 半锁存缓冲器设计可以提供增加的速度而不显着增加功耗。

公开(公告)号：US08643108B2

公开(公告)日：2014-02-04

申请号：US13214102

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/761 ,  H01L29/66795

摘要： One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及缓冲晶体管器件。 该器件包括形成在半导体衬底中的缓冲的垂直鳍状结构。 垂直鳍状结构至少包括上半导体层，缓冲区和阱区​​的至少一部分。 缓冲区具有第一掺杂极性，并且阱区具有与第一掺杂极性相反的第二掺杂极性。 在缓冲区和阱区​​之间形成至少部分覆盖垂直鳍状结构的水平横截面的至少一个p-n结。 还公开了其它实施例，方面和特征。

公开(公告)号：US20070113106A1

公开(公告)日：2007-05-17

申请号：US11282858

申请日：2005-11-17

申请人： Lin-Shih Liu ,  Mark Chan

发明人： Lin-Shih Liu ,  Mark Chan

IPC分类号： G06F1/26

CPC分类号： G06F1/3225

摘要： Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

摘要翻译： 提供具有存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 当加载配置数据时，存储器元件产生施加到可编程逻辑器件中的晶体管的栅极的输出信号以定制可编程逻辑。 为了确保可编程逻辑中的晶体管正确接通，在正常设备操作期间，存储器元件由提供的电源电平供电。 在数据加载操作期间，存储器元件的电源电平降低。 在加载期间降低存储元件电源电平增加了存储器元件的写入裕度。

公开(公告)号：US20070109017A1

公开(公告)日：2007-05-17

申请号：US11282437

申请日：2005-11-17

申请人： Lin-Shih Liu ,  Mark Chan ,  Toan Do

发明人： Lin-Shih Liu ,  Mark Chan ,  Toan Do

IPC分类号： H03K19/177

CPC分类号： G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

摘要： Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

摘要翻译： 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US08369175B1

公开(公告)日：2013-02-05

申请号：US12874152

申请日：2010-09-01

申请人： Lin-Shih Liu ,  Andy L. Lee ,  Ping-Chen Liu ,  Irfan Rahim ,  Srinivas Perisetty

发明人： Lin-Shih Liu ,  Andy L. Lee ,  Ping-Chen Liu ,  Irfan Rahim ,  Srinivas Perisetty

IPC分类号： G11C5/14

CPC分类号： G11C11/412 ,  G11C15/04

摘要： Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.

摘要翻译： 集成电路可以包括具有电压过应力保护的存储器元件。 存储单元的一种合适布置可以包括具有两个交叉耦合的反相器的锁存器。 两个交叉耦合反相器中的每一个可以耦合在第一和第二电源线之间，并且可以包括具有连接到单独的电源线的栅极的晶体管。 另一种合适的存储单元布置可以包括三个交叉耦合电路。 三个电路中的两个可以由第一正电源线供电，而剩余电路可以由第二正电源线供电。 这些存储单元可用于向对应的通道提供升高的正静态控制信号和降低的地面静态控制信号。 这些存储单元可以包括在读/写操作期间使用的存取晶体管和读缓冲电路。