公开(公告)号：US07995375B2

公开(公告)日：2011-08-09

申请号：US12169598

申请日：2008-07-08

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC分类号： G11C11/00

CPC分类号： G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

摘要： Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

摘要翻译： 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US07385423B1

公开(公告)日：2008-06-10

申请号：US11114827

申请日：2005-04-26

申请人： Lin-Shih Liu ,  Mark T Chan

发明人： Lin-Shih Liu ,  Mark T Chan

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/01721

摘要： A low-power low-voltage buffer with a half-latch is provided. The half-latch buffer design may provide increased speed without dramatically increasing power consumption.

摘要翻译： 提供具有半锁存器的低功率低电压缓冲器。 半锁存缓冲器设计可以提供增加的速度而不显着增加功耗。

公开(公告)号：US07430148B2

公开(公告)日：2008-09-30

申请号：US11282858

申请日：2005-11-17

申请人： Lin-Shih Liu ,  Mark T. Chan

发明人： Lin-Shih Liu ,  Mark T. Chan

IPC分类号： G11C5/14

CPC分类号： G06F1/3225

摘要： Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

摘要翻译： 提供具有存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 当加载配置数据时，存储器元件产生施加到可编程逻辑器件中的晶体管的栅极的输出信号以定制可编程逻辑。 为了确保可编程逻辑中的晶体管正确接通，在正常设备操作期间，存储器元件由提供的电源电平供电。 在数据加载操作期间，存储器元件的电源电平降低。 在加载期间降低存储元件电源电平增加了存储器元件的写入裕度。

公开(公告)号：US07411853B2

公开(公告)日：2008-08-12

申请号：US11282437

申请日：2005-11-17

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

摘要： Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

摘要翻译： 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US07277351B2

公开(公告)日：2007-10-02

申请号：US11335437

申请日：2006-01-18

申请人： Lin-Shih Liu ,  Mark T. Chan

发明人： Lin-Shih Liu ,  Mark T. Chan

IPC分类号： G11C5/14

CPC分类号： H03K19/1776 ,  H03K19/17784

摘要： Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

摘要翻译： 提供可编程逻辑器件集成电路。 可编程逻辑器件集成电路包含以可编程核心逻辑电源电压供电的可编程核心逻辑。 可编程逻辑器件配置数据被加载到存储器元件中以配置可编程核心逻辑以执行定制逻辑功能。 在正常操作期间，存储器元件可以用大于可编程核心逻辑电源电压的电源电压供电。 在数据加载操作期间，存储器元件可以由等于可编程核心逻辑电源电压的电源电压供电。 数据加载和读取电路将数据加载到存储器元件中并从存储器元件读取数据。 数据加载和读取电路产生地址信号。 在数据写入操作期间，地址信号可能具有比读取操作期间更大的电压电平。

公开(公告)号：US09245592B2

公开(公告)日：2016-01-26

申请号：US13204466

申请日：2011-08-05

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC分类号： G11C5/14 ,  G11C11/413 ,  G05F1/46 ,  H03K19/177

CPC分类号： G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

摘要： Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

摘要翻译： 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US08611137B2

公开(公告)日：2013-12-17

申请号：US13304226

申请日：2011-11-23

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

IPC分类号： G11C11/00

CPC分类号： G11C11/52 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H1/0094 ,  H01H1/20 ,  H01H59/0009 ,  H01L27/101 ,  H01L27/11

摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

摘要翻译： 提供具有存储元件的集成电路。 集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分， 中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。 第一和第二部分中的装置可以接收相应的电源电压。 在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。 在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。 第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。 以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

公开(公告)号：US08411491B1

公开(公告)日：2013-04-02

申请号：US12983816

申请日：2011-01-03

申请人： Lin-Shih Liu ,  Mark T. Chan

发明人： Lin-Shih Liu ,  Mark T. Chan

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C5/147 ,  G11C7/12 ,  G11C7/20

摘要： Memory elements may be provided that include bi-stable data storage elements based on cross-coupled inverters. A pair of address transistors may be used to implement a differential data writing scheme for the memory elements. One of the address transistors may be coupled between a first data line and a first data storage node in each memory element and another of the address transistors may be coupled between a second data line and a second data storage node. A read circuit may be coupled to the second data storage node. Clear transistors may be interspersed through the array. The clear transistors may help pull the data lines to desired voltages during clear operations. An adjustable power supply may supply a weakened power supply voltage to a pull-up clear transistor and to the first and second inverters during clear operations.

摘要翻译： 可以提供包括基于交叉耦合的逆变器的双稳态数据存储元件的存储器元件。 可以使用一对地址晶体管来实现用于存储器元件的差分数据写入方案。 地址晶体管中的一个可以耦合在每个存储器元件中的第一数据线和第一数据存储节点之间，另一个地址晶体管可以耦合在第二数据线和第二数据存储节点之间。 读取电路可以耦合到第二数据存储节点。 透明晶体管可以散布在阵列中。 在清除操作期间，透明晶体管可以帮助将数据线拉到期望的电压。 可调电源可以在清除操作期间向上拉清除晶体管和第一和第二逆变器提供弱化的电源电压。

公开(公告)号：US20110285422A1

公开(公告)日：2011-11-24

申请号：US13204466

申请日：2011-08-05

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC分类号： H03K19/173

CPC分类号： G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

摘要： Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

摘要翻译： 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US07358764B1

公开(公告)日：2008-04-15

申请号：US11449944

申请日：2006-06-09

申请人： Mark T. Chan ,  Lin-Shih Liu

发明人： Mark T. Chan ,  Lin-Shih Liu

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C7/20 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17784

摘要： Integrated circuits such as programmable logic device integrated circuits have arrays of memory elements into which configuration data is loaded. The memory elements are formed form a pair of independently-powered cross-coupled inverters. Control circuitry generates a first inverter power supply signal and a second inverter power supply signal. The first and second inverter power supply signals are distributed to the inverters in the memory elements using pairs of inverter power distribution paths. When it is desired to reset the memory elements, the control circuitry takes the second power supply signal high before the first power supply signal. When it is desired to preset the memory elements, the control circuitry takes the second power supply high after the first power supply signal.

摘要翻译： 诸如可编程逻辑器件集成电路的集成电路具有加载配置数据的存储器元件阵列。 存储元件由一对独立供电的交叉耦合逆变器形成。 控制电路产生第一反相器电源信号和第二反相器电源信号。 第一和第二逆变器电源信号使用成对的逆变器配电路径分配到存储元件中的反相器。 当希望复位存储器元件时，控制电路在第一电源信号之前使第二电源信号为高电平。 当希望预置存储元件时，控制电路在第一电源信号之后使第二电源为高电平。