公开(公告)号：US07995375B2

公开(公告)日：2011-08-09

申请号：US12169598

申请日：2008-07-08

Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC: G11C11/00

CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US09245592B2

公开(公告)日：2016-01-26

申请号：US13204466

申请日：2011-08-05

Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC: G11C5/14 ,  G11C11/413 ,  G05F1/46 ,  H03K19/177

CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US08611137B2

公开(公告)日：2013-12-17

申请号：US13304226

申请日：2011-11-23

Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

IPC: G11C11/00

CPC classification number: G11C11/52 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H1/0094 ,  H01H1/20 ,  H01H59/0009 ,  H01L27/101 ,  H01L27/11

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

Abstract translation: 提供具有存储元件的集成电路。 集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分， 中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。 第一和第二部分中的装置可以接收相应的电源电压。 在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。 在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。 第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。 以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

公开(公告)号：US08411491B1

公开(公告)日：2013-04-02

申请号：US12983816

申请日：2011-01-03

Applicant: Lin-Shih Liu ,  Mark T. Chan

Inventor： Lin-Shih Liu ,  Mark T. Chan

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C7/1048 ,  G11C5/147 ,  G11C7/12 ,  G11C7/20

Abstract: Memory elements may be provided that include bi-stable data storage elements based on cross-coupled inverters. A pair of address transistors may be used to implement a differential data writing scheme for the memory elements. One of the address transistors may be coupled between a first data line and a first data storage node in each memory element and another of the address transistors may be coupled between a second data line and a second data storage node. A read circuit may be coupled to the second data storage node. Clear transistors may be interspersed through the array. The clear transistors may help pull the data lines to desired voltages during clear operations. An adjustable power supply may supply a weakened power supply voltage to a pull-up clear transistor and to the first and second inverters during clear operations.

Abstract translation: 可以提供包括基于交叉耦合的逆变器的双稳态数据存储元件的存储器元件。 可以使用一对地址晶体管来实现用于存储器元件的差分数据写入方案。 地址晶体管中的一个可以耦合在每个存储器元件中的第一数据线和第一数据存储节点之间，另一个地址晶体管可以耦合在第二数据线和第二数据存储节点之间。 读取电路可以耦合到第二数据存储节点。 透明晶体管可以散布在阵列中。 在清除操作期间，透明晶体管可以帮助将数据线拉到期望的电压。 可调电源可以在清除操作期间向上拉清除晶体管和第一和第二逆变器提供弱化的电源电压。

公开(公告)号：US20110285422A1

公开(公告)日：2011-11-24

申请号：US13204466

申请日：2011-08-05

Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC: H03K19/173

CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

公开(公告)号：US07358764B1

公开(公告)日：2008-04-15

申请号：US11449944

申请日：2006-06-09

Applicant: Mark T. Chan ,  Lin-Shih Liu

Inventor： Mark T. Chan ,  Lin-Shih Liu

IPC: G11C5/14

CPC classification number: G11C11/419 ,  G11C7/20 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17784

Abstract: Integrated circuits such as programmable logic device integrated circuits have arrays of memory elements into which configuration data is loaded. The memory elements are formed form a pair of independently-powered cross-coupled inverters. Control circuitry generates a first inverter power supply signal and a second inverter power supply signal. The first and second inverter power supply signals are distributed to the inverters in the memory elements using pairs of inverter power distribution paths. When it is desired to reset the memory elements, the control circuitry takes the second power supply signal high before the first power supply signal. When it is desired to preset the memory elements, the control circuitry takes the second power supply high after the first power supply signal.

Abstract translation: 诸如可编程逻辑器件集成电路的集成电路具有加载配置数据的存储器元件阵列。 存储元件由一对独立供电的交叉耦合逆变器形成。 控制电路产生第一反相器电源信号和第二反相器电源信号。 第一和第二逆变器电源信号使用成对的逆变器配电路径分配到存储元件中的反相器。 当希望复位存储器元件时，控制电路在第一电源信号之前使第二电源信号为高电平。 当希望预置存储元件时，控制电路在第一电源信号之后使第二电源为高电平。

公开(公告)号：US20130127494A1

公开(公告)日：2013-05-23

申请号：US13304226

申请日：2011-11-23

Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

IPC: H03K19/177 ,  G11C11/52

CPC classification number: G11C11/52 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H1/0094 ,  H01H1/20 ,  H01H59/0009 ,  H01L27/101 ,  H01L27/11

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

Abstract translation: 提供具有存储元件的集成电路。 集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分， 中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。 第一和第二部分中的装置可以接收相应的电源电压。 在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。 在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。 第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。 以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

公开(公告)号：US07911826B1

公开(公告)日：2011-03-22

申请号：US12057343

申请日：2008-03-27

Applicant: Lin-Shih Liu ,  Mark T. Chan

Inventor： Lin-Shih Liu ,  Mark T. Chan

IPC: G11C5/14 ,  G11C11/41 ,  G11C11/413

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/413

Abstract: Integrated circuits are provided that have memory elements. The memory elements may be organized in an array. Data such as programmable logic device configuration data may be loaded into the array using read and write control circuitry. Each memory element may store data using a pair of cross-coupled inverters. Power supply circuitry may be used to power the cross-coupled inverters. A positive power supply signal and a ground power supply signal may be provided to the inverters by the power supply circuitry. Each memory element may have an associated clear transistor. A clear control signal may be asserted to turn on the clear transistor when clearing the memory elements. A given one of the inverters in each memory element may be momentarily weakened with respect to the clear transistor in that memory element by using the power supply circuitry to temporarily elevate the ground power supply signal.

Abstract translation: 提供具有存储元件的集成电路。 存储器元件可以被组织成阵列。 诸如可编程逻辑器件配置数据的数据可以使用读和写控制电路加载到阵列中。 每个存储元件可以使用一对交叉耦合的反相器存储数据。 电源电路可用于为交叉耦合的逆变器供电。 正电源信号和接地电源信号可以由电源电路提供给逆变器。 每个存储元件可以具有相关联的清除晶体管。 当清除存储元件时，可以断言清除控制信号以打开清除晶体管。 通过使用电源电路临时提升接地电源信号，每个存储元件中的给定一个反相器可能相对于该存储元件中的透明晶体管瞬间减弱。

公开(公告)号：US07768818B1

公开(公告)日：2010-08-03

申请号：US12057339

申请日：2008-03-27

Applicant: Mark T. Chan ,  Lin-Shih Liu

Inventor： Mark T. Chan ,  Lin-Shih Liu

IPC: G11C7/00

CPC classification number: H03K19/1778 ,  G11C11/412

Abstract: Memory elements for integrated circuit are provided that have efficient transistor layouts. The integrated circuits may be programmable logic device integrated circuits on which memory elements are formed into arrays. Each memory element may have a pair of cross-coupled inverters, an address transistor, and a clear transistor. The transistors in each memory element may be formed from n-type and p-type semiconductor regions that are crossed by only three gate conductor fingers. Programmable transistors on the integrated circuit may be controlled by static output signals from the memory elements. The programmable transistors may be used to form multiplexers. The multiplexers may be formed from n-type regions that are crossed by only three gate fingers each. The gate fingers of the multiplexers may be aligned with the gate fingers of the transistor structures of the memory elements.

Abstract translation: 提供了具有有效晶体管布局的集成电路的存储元件。 集成电路可以是其上存储元件形成阵列的可编程逻辑器件集成电路。 每个存储元件可以具有一对交叉耦合的反相器，地址晶体管和透明晶体管。 每个存储元件中的晶体管可以由仅由三个栅极导体指状物交叉的n型和p型半导体区域形成。 集成电路上的可编程晶体管可以由来自存储器元件的静态输出信号来控制。 可编程晶体管可用于形成多路复用器。 多路复用器可以由仅由三个栅极指指交叉的n型区域形成。 多路复用器的栅极指可以与存储器元件的晶体管结构的栅极指状对准。

公开(公告)号：US20080266997A1

公开(公告)日：2008-10-30

申请号：US12169598

申请日：2008-07-08

Applicant: Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Toan D. Do

IPC: G11C5/14 ,  H03K19/173

CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。