公开(公告)号：US09213630B2

公开(公告)日：2015-12-15

申请号：US13399587

申请日：2012-02-17

申请人： Vinod Lakhani ,  Benjamin Louie

发明人： Vinod Lakhani ,  Benjamin Louie

IPC分类号： G06F12/00 ,  G06F12/02 ,  G11C29/00 ,  G11C16/04

CPC分类号： G06F12/0246 ,  G11C16/04 ,  G11C29/76 ,  G11C29/808 ,  G11C29/82

摘要： An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

公开(公告)号：US08145832B2

公开(公告)日：2012-03-27

申请号：US13035580

申请日：2011-02-25

申请人： Vinod Lakhani ,  Benjamin Louie

发明人： Vinod Lakhani ,  Benjamin Louie

IPC分类号： G06F13/00

CPC分类号： G06F12/0246 ,  G11C16/04 ,  G11C29/76 ,  G11C29/808 ,  G11C29/82

摘要： An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

摘要翻译： 描述了一种改进的非易失性擦除块存储器件装置和方法，其包括改进的寻址方案以提供扩展寻址，以允许不用于修复要被访问和利用的主存储器阵列的一般使用擦除块的冗余擦除块作为 最终用户额外的存储空间。 由未使用的冗余擦除块形成的附加存储空间和主存储器阵列的指定存储空间作为单个相邻地址空间呈现给终端用户。 此外，冗余擦除块可以用于修复非易失性擦除块存储器或闪存设备的存储器阵列中的任何损坏的擦除块，而不管银行放置。

公开(公告)号：US08024629B2

公开(公告)日：2011-09-20

申请号：US12767020

申请日：2010-04-26

申请人： Benjamin Louie ,  Scott N. Gatzemeier ,  Adam Johnson ,  Frankie F. Roohparvar

发明人： Benjamin Louie ,  Scott N. Gatzemeier ,  Adam Johnson ,  Frankie F. Roohparvar

IPC分类号： G11C29/00

CPC分类号： G01R31/318547 ,  G11C29/1201 ,  G11C29/40 ,  G11C29/48 ,  G11C2029/3202

摘要： An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.

摘要翻译： 用于测试存储器阵列和/或逻辑电路的I / O压缩装置包括从存储器阵列/逻辑电路输出压缩测试数据的可选压缩电路。 I / O扫描寄存器耦合到每个I / O焊盘，用于响应于测试模式选择信号，测试数据输入和测试时钟将串行数据转换为并行数据到并行数据。

公开(公告)号：US20100142280A1

公开(公告)日：2010-06-10

申请号：US12703901

申请日：2010-02-11

申请人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

发明人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US07505357B2

公开(公告)日：2009-03-17

申请号：US11508325

申请日：2006-10-11

申请人： Vinod Lakhani ,  Benjamin Louie

发明人： Vinod Lakhani ,  Benjamin Louie

IPC分类号： G11C8/00

CPC分类号： G11C29/76 ,  G11C29/789

摘要： A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.

摘要翻译： 公开了一种用于缺陷存储器列或行替代的方案，其使用可编程查找表来存储当接收到某些列或行地址时用于列选择的新地址。 每当在输入地址中检测到地址转换时，新的地址被加载到可编程熔丝锁存器中。

公开(公告)号：US20080074933A1

公开(公告)日：2008-03-27

申请号：US11515629

申请日：2006-09-05

申请人： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

发明人： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G11C7/10

CPC分类号： G11C7/1042 ,  G11C7/1051 ,  G11C16/26 ,  G11C2207/2245

摘要： A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

摘要翻译： 描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。 这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间 感测和数据I / O。

公开(公告)号：US07345924B2

公开(公告)日：2008-03-18

申请号：US11546171

申请日：2006-10-11

申请人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

发明人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US07336537B2

公开(公告)日：2008-02-26

申请号：US11487857

申请日：2006-07-17

申请人： Benjamin Louie ,  Aaron Yip

发明人： Benjamin Louie ,  Aaron Yip

IPC分类号： G11C16/06

CPC分类号： G11C29/832 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/26 ,  G11C29/789 ,  G11C29/82 ,  G11C2029/4402

摘要： Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.

公开(公告)号：US20070133294A1

公开(公告)日：2007-06-14

申请号：US11675151

申请日：2007-02-15

申请人： Jin-Man Han ,  Benjamin Louie

发明人： Jin-Man Han ,  Benjamin Louie

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/3427

摘要： The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

摘要翻译： 用于减少闪速存储器阵列中的编程干扰的方法在编程电压下偏置所选择的字线。 未选择的字线之一，比所选择的字线更接近阵列地，被偏置在小于V 的电压。 在这个未被选择的字线上被偏置在该电压下的存储器单元阻挡栅极引起的漏极从阵列中的细胞进一步上升。 剩余的未选择的字线偏向V 。 在另一个实施例中，第二源选择栅极线被添加到阵列。 最靠近字线的源选择栅极线被偏置在小于V 的电压，以便阻挡来自阵列的栅感应漏极泄漏。

公开(公告)号：US20070038800A1

公开(公告)日：2007-02-15

申请号：US11581887

申请日：2006-10-17

申请人： Vinod Lakhani ,  Benjamin Louie

发明人： Vinod Lakhani ,  Benjamin Louie

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G11C16/04 ,  G11C29/76 ,  G11C29/808 ,  G11C29/82

摘要： An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

摘要翻译： 描述了一种改进的非易失性擦除块存储器件装置和方法，其包括改进的寻址方案以提供扩展寻址，以允许不用于修复要被访问和利用的主存储器阵列的一般使用擦除块的冗余擦除块作为 最终用户额外的存储空间。 由未使用的冗余擦除块形成的附加存储空间和主存储器阵列的指定存储空间作为单个相邻地址空间呈现给终端用户。 此外，冗余擦除块可以用于修复非易失性擦除块存储器或闪存设备的存储器阵列中的任何损坏的擦除块，而不管银行放置。