公开(公告)号：US5821794A

公开(公告)日：1998-10-13

申请号：US626043

申请日：1996-04-01

申请人： Hagop Nazarian ,  Donald A. Krall ,  S. Babar Raza

发明人： Hagop Nazarian ,  Donald A. Krall ,  S. Babar Raza

IPC分类号： H03K19/177 ,  H03K1/04

CPC分类号： H03K19/1774

摘要： The present invention provides a clocking circuit allowing individual macrocells in a particular macrocell block of a CPLD to use different polarities of the same clock. The input clock pin can now drive all the macrocells directly, which can eliminate additional buffering states and improve the clock to out timing, Tco, by (for example) 300 ps. The clocks are presented directly to the clock selection multiplexers for each macrocell. Additional functioning may be realized by implementing additional configuration bits inside the clocking architecture.

摘要翻译： 本发明提供了一种时钟电路，其允许CPLD的特定宏小区块中的各个宏小区使用相同时钟的不同极性。 输入时钟引脚现在可以直接驱动所有宏单元，这可以消除额外的缓冲状态，并通过（例如）300 ps将时钟转换为时序Tco。 时钟直接显示给每个宏单元的时钟选择多路复用器。 额外的功能可以通过在时钟架构内实现附加配置位来实现。

公开(公告)号：US5654652A

公开(公告)日：1997-08-05

申请号：US534358

申请日：1995-09-27

申请人： S. Babar Raza ,  Hagop Nazarian

发明人： S. Babar Raza ,  Hagop Nazarian

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0948

CPC分类号： H03K19/00361

摘要： A high speed ratio CMOS logic structure includes a static PMOS pullup transistor connected to an output node, and a plurality of NMOS pulldown transistors, connected in parallel, to the output node and which collectively define a pulldown circuit. The pullup transistor is biased using a reference voltage to define a static pullup strength for the logic structure. The pulldown strength of the pulldown circuit is also fixed. The combination of the pullup transistor, and the pulldown transistors define an N input NOR gate. The logic structure, however, further includes a feedback logic circuit, formed by a pair of inverters connected in series coupled to the output node to sense a current logic state of the output node. The feedback logic circuit generates an enable signal that is provided to a second, dynamic PMOS transistor connected in parallel with the static pullup PMOS transistor. When the logic state on the output node is low, the feedback logic circuit generates a low signal, which activates the dynamic PMOS transistor into a conductive state, thus increasing the pullup strength of the logic structure. This increased pullup strength provides for an improved switching for the next logic state transition: low-to-high. Once the output node has transitioned to the logic high state, and after a fixed time delay, the feedback logic circuit generates a logic high signal, which turns off the dynamic PMOS transistor, which weakens the pullup strength of the logic structure. In view of this weakened pullup strength, the next logic state transition of the output node--high-to-low--is accomplished much faster.

摘要翻译： 高速比CMOS逻辑结构包括连接到输出节点的静态PMOS上拉晶体管和并联连接到输出节点并且共同定义下拉电路的多个NMOS下拉晶体管。 使用参考电压对上拉晶体管进行偏置，以定义逻辑结构的静态上拉强度。 下拉电路的下拉强度也是固定的。 上拉晶体管和下拉晶体管的组合限定了N个输入NOR门。 然而，逻辑结构还包括反馈逻辑电路，其由串联耦合到输出节点的一对反相器形成，以感测输出节点的当前逻辑状态。 反馈逻辑电路产生提供给与静态上拉PMOS晶体管并联连接的第二动态PMOS晶体管的使能信号。 当输出节点上的逻辑状态为低电平时，反馈逻辑电路产生一个低电平信号，这个信号将动态PMOS晶体管激活成导通状态，从而增加了逻辑结构的上拉电阻。 这种增加的上拉强度为下一个逻辑状态转换提供了一个改进的切换：从低到高。 一旦输出节点转变到逻辑高电平状态，并且在固定的时间延迟之后，反馈逻辑电路产生逻辑高电平信号，这将关闭动态PMOS晶体管，这削弱了逻辑结构的上拉电阻。 鉴于这种上拉强度的削弱，输出节点的下一个逻辑状态转换 - 从高到低实现得快得多。

公开(公告)号：US5986489A

公开(公告)日：1999-11-16

申请号：US627946

申请日：1996-04-03

申请人： S. Babar Raza ,  Lin-Shih Liu ,  Hagop Nazarian

发明人： S. Babar Raza ,  Lin-Shih Liu ,  Hagop Nazarian

IPC分类号： H03K19/003 ,  H03K5/12

CPC分类号： H03K19/00361

摘要： A slew rate control circuit to control output slew rate according to a programmable reference signal. A slew rate control circuit limits the slew rate of a plurality output buffers according to a signal received from a programmable slew rate control reference.

摘要翻译： 一种转换速率控制电路，用于根据可编程参考信号来控制输出转换速率。 压摆率控制电路根据从可编程转换速率控制基准接收到的信号来限制多个输出缓冲器的转换速率。

公开(公告)号：US08796658B1

公开(公告)日：2014-08-05

申请号：US13466008

申请日：2012-05-07

申请人： Hagop Nazarian ,  Sung Hyun Jo

发明人： Hagop Nazarian ,  Sung Hyun Jo

IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L45/1641 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/148 ,  H01L45/165 ,  H01L45/1675

摘要： A resistive memory device includes a first metallic layer comprising a source of positive metallic ions, a switching media having an upper surface and a lower surface, wherein the upper surface is adjacent to the first metallic layer, wherein the switching media comprises conductive filaments comprising positive metallic ions from the source of positive metallic ions formed from the upper surface towards the lower surface, a semiconductor substrate, a second metallic layer disposed above the semiconductor substrate, a non-metallic conductive layer disposed above the second metallic layer, and an interface region between the non-metallic conductive layer and the switching media having a negative ionic charge.

摘要翻译： 电阻式存储器件包括包含正金属离子源的第一金属层，具有上表面和下表面的开关介质，其中上表面与第一金属层相邻，其中开关介质包括包含正极的导电细丝 从上表面朝向下表面形成的正金属离子源的金属离子，半导体衬底，设置在半导体衬底上方的第二金属层，设置在第二金属层上方的非金属导电层，以及界面区域 在非金属导电层和具有负离子电荷的开关介质之间。

公开(公告)号：US08723154B2

公开(公告)日：2014-05-13

申请号：US12894057

申请日：2010-09-29

申请人： Sung Hyun Jo ,  Hagop Nazarian

发明人： Sung Hyun Jo ,  Hagop Nazarian

IPC分类号： H01L29/12 ,  H01L29/8605 ,  H01L27/105 ,  H01L21/8239

CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

摘要： An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device.

摘要翻译： 集成电路器件。 集成电路器件包括具有表面区域的半导体衬底。 栅极电介质层覆盖在衬底的表面区域上。 该器件包括具有p +有源区的MOS器件。 p +有源区形成用于电阻式开关器件的第一电极。 电阻开关器件包括覆盖p +有源区的非晶硅开关材料和覆盖在第一金属导体结构上的金属电极。 金属电极包括金属材料，当对金属电极施加正偏压时，在非晶硅开关材料中形成金属区域。 MOS器件为集成电路器件提供选择晶体管。

公开(公告)号：US20130024742A1

公开(公告)日：2013-01-24

申请号：US13616379

申请日：2012-09-14

申请人： Hagop Nazarian ,  Ping Hou

发明人： Hagop Nazarian ,  Ping Hou

IPC分类号： H03M13/29

CPC分类号： G06F11/1072 ,  G11C2029/0411

摘要： Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

摘要翻译： 本文描述了提供电子存储器的单位和多位纠错。 作为示例，可以通过在一组分析的存储器单元的位级分布之间建立可疑区域来实现纠错。 可疑区域可以定义分布的潜在错误位。 如果对于分布检测到位错误，则可以首先将错误校正应用于可疑区域中的潜在错误位。 通过识别怀疑的错误位并将初始误差修正限制在这种识别的位上，可以减轻或避免对分布的所有位应用纠错所涉及的复杂性，从而提高电子存储器误码校正的效率。

公开(公告)号：US20120327717A1

公开(公告)日：2012-12-27

申请号：US13600527

申请日：2012-08-31

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C16/26 ,  H01L27/088 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US20120236650A1

公开(公告)日：2012-09-20

申请号：US13051296

申请日：2011-03-18

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C16/04 ,  G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C16/0483 ,  G11C2213/33 ,  G11C2213/53 ,  G11C2213/56 ,  G11C2213/75

摘要： A non-volatile memory device includes a first select transistor, a second select transistor, and a first string of first memory cells provided between the first and second select transistors. Each first memory cell has a first resistive memory cell and a first transistor. The first resistive memory cell is in series with a gate of the first transistor. The non-volatile memory device further includes a first bit line coupled to a drain of the first select transistor and a plurality of word lines. Each word line is coupled to one of the first memory cells.

摘要翻译： 非易失性存储器件包括第一选择晶体管，第二选择晶体管和设置在第一和第二选择晶体管之间的第一存储单元串。 每个第一存储单元具有第一电阻存储单元和第一晶体管。 第一电阻存储单元与第一晶体管的栅极串联。 非易失性存储器件还包括耦合到第一选择晶体管的漏极和多个字线的第一位线。 每个字线耦合到第一存储器单元之一。

公开(公告)号：US20110317466A1

公开(公告)日：2011-12-29

申请号：US12824352

申请日：2010-06-28

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C5/06 ,  H01L21/82

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US20090109758A1

公开(公告)日：2009-04-30

申请号：US11929761

申请日：2007-10-30

申请人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

发明人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0491

摘要： A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.

摘要翻译： 一种包括程序组件的系统，该程序组件使用FN隧道对一组或多个NVM单元阵列的一个或多个非易失性存储器（“NVM”）单元进行编程，所述擦除组件擦除所述NVM单元阵列的一对或多个NVM单元 使用FN隧道的NVM单元，以及读取组件，其读取NVM单元阵列阵列中的一个或多个NVM单元。