公开(公告)号：US12057487B2

公开(公告)日：2024-08-06

申请号：US18357761

申请日：2023-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon Jhy Liaw

IPC: H01L29/423 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H10B10/00

CPC classification number: H01L29/42392 ,  H01L27/0207 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H10B10/12 ,  H10B10/18

Abstract: An exemplary semiconductor memory chip includes a first static random access memory (SRAM) cell and a second SRAM cell. The first SRAM cell has a first GAA transistor, and the second SRAM cell has a second GAA transistor. The first and the second SRAM cells have a same cell size, and the first and the second GAA transistors are of a same transistor type. Moreover, the first GAA transistor has a first threshold voltage and the second GAA transistor has a second threshold voltage. The second threshold voltage is different than the first threshold voltage. Furthermore, the first GAA transistor has a first gate stack and the second GAA transistor has a second gate stack. The first gate stack has a first work function value, and the second gate stack has a second work function value. The second work function value is different than the first work function value.

公开(公告)号：US20240260248A1

公开(公告)日：2024-08-01

申请号：US18608045

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Wen-Chun Keng ,  Lien Jung Hung

IPC: H10B10/00

CPC classification number: H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes a first transistor and a well strap feature disposed over a doped region of a first type dopant. The first transistor includes a first gate structure engaging a first channel region and a first epitaxial feature abutting the first channel region. The well-strap feature incudes a plurality of first nanostructures vertically stacked, a second gate structure wrapping around each of the first nanostructures, and a second epitaxial feature abutting the first nanostructures. The well-strap feature is configured to bias the doped region by electrically connecting the second epitaxial feature to a bias voltage.

公开(公告)号：US20240258113A1

公开(公告)日：2024-08-01

申请号：US18612807

申请日：2024-03-21

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Fee Li Lie ,  Dongbing Shao ,  Robert C. Wong ,  Yongan Xu

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/12 ,  H10B10/18

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

公开(公告)号：US12052851B2

公开(公告)日：2024-07-30

申请号：US17885166

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gulbagh Singh ,  Shun-Chi Tsai ,  Chih-Ming Lee ,  Chi-Yen Lin ,  Kuo-Hung Lo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H10B10/00 ,  G11C11/412 ,  H01L27/02

CPC classification number: H10B10/12 ,  H01L21/823475 ,  H01L29/0649 ,  H01L29/4238 ,  G11C11/412 ,  H01L27/0207

Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.

公开(公告)号：US12048136B2

公开(公告)日：2024-07-23

申请号：US18178723

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon-Jhy Liaw

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66545

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric fin and a second dielectric fin over a substrate, a first semiconductor fin between the first dielectric fin and the second dielectric fin, and an insulating liner surrounding a lower portion of the first dielectric fin, a lower portion of the first semiconductor fin, and a lower portion of the second dielectric fin. The semiconductor structure also includes a first gate electrode surrounding an upper portion of the first dielectric fin and an upper portion of the first semiconductor fin.

公开(公告)号：US20240234311A1

公开(公告)日：2024-07-11

申请号：US18610267

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L23/528 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827 ,  H10B10/12

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

公开(公告)号：US12035517B2

公开(公告)日：2024-07-09

申请号：US17125683

申请日：2020-12-17

Applicant: Arm Limited

Inventor： Amit Chhabra ,  David Victor Pietromonaco

IPC: H10B10/00 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/06 ,  H01L27/092

CPC classification number: H10B10/12 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0922

Abstract: Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.

公开(公告)号：US20240221827A1

公开(公告)日：2024-07-04

申请号：US18137620

申请日：2023-04-21

Applicant: Invention and Collaboration Laboratory, Inc.

Inventor： Chao-Chun LU

IPC: G11C11/412 ,  H10B10/00

CPC classification number: G11C11/412 ,  H10B10/12

Abstract: A CMOS SRAM structure includes a Bulk semiconductor substrate with a PMOS active region and an NMOS active region. A set of PMOS transistors are formed in the PMOS active region and a set of NMOS transistors are formed in the NMOS active region. A VDD contacting line is electrically coupled to the set of PMOS transistors, a VSS contacting line is electrically coupled to the set of NMOS transistors, a word line is electrically coupled to the set of NMOS transistors, a bit line is electrically coupled to the set of NMOS transistors, and a complementary bit line is electrically coupled to the set of NMOS transistors. Wherein either the PMOS active region or the NMOS active region is a SOI region which is fully isolated from a rest portion of the Bulk semiconductor substrate which does not include the PMOS active region and the NMOS active region.

公开(公告)号：US12029021B2

公开(公告)日：2024-07-02

申请号：US17701419

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Peng Zheng ,  Varun Mishra ,  Tahir Ghani

IPC: H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US20240213154A1

公开(公告)日：2024-06-27

申请号：US18599049

申请日：2024-03-07

Applicant: Intel Corporation

Inventor： Smita SHRIDHARAN ,  Zheng GUO ,  Eric A. KARL ,  George SHCHUPAK ,  Tali KOSINOVSKY

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H10B10/00

CPC classification number: H01L23/528 ,  H01L23/535 ,  H01L27/0924 ,  H10B10/12

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.