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    Selection of logic paths for redundancy
    16.
    发明授权
    Selection of logic paths for redundancy 有权
    选择冗余的逻辑路径

    公开(公告)号：US09484919B1

    公开(公告)日：2016-11-01

    申请号：US14266547

    申请日：2014-04-30

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain ,  Pierre Maillard ,  James Karp ,  Michael J. Hart

    IPC: H03K19/003

    CPC classification number: H03K19/00392

    Abstract: Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.

    Abstract translation: 公开了用于处理电路设计以防止单个事件扰乱的方法。 基于逻辑路径中的电路元件的故障率的总和大于逻辑路径的故障率的目标降低与投票电路的故障率的乘积的总和，选择电路设计的逻辑路径用于冗余。 电路设计被修改为包括并联耦合的逻辑路径的至少三个实例和耦合以从逻辑路径的实例接收输出信号的投票电路。 修改后的电路设计存储在存储器中。

    Programmable integrated circuit having different types of configuration memory
    17.
    发明授权
    Programmable integrated circuit having different types of configuration memory 有权
    具有不同类型配置存储器的可编程集成电路

    公开(公告)号：US09275180B1

    公开(公告)日：2016-03-01

    申请号：US14330922

    申请日：2014-07-14

    Applicant: Xilinx, Inc.

    Inventor： James Karp

    IPC: G06F17/50 ,  H03K19/0175

    CPC classification number: G06F17/5054 ,  G06F11/183 ,  H03K19/017581 ,  H03K19/1776 ,  H03K19/17764

    Abstract: To implement a circuit design on a programmable integrated circuit (IC), first data are generated for implementing the circuit design. Critical and non-critical portions of the circuit design are determined, and second data are generated for programming configuration memory cells of the programmable IC to implement the circuit design. A first subset of the second data is assigned to program a first type of configuration memory cells to implement the critical portion of the circuit design on a first subset of programmable logic resources and a first subset of programmable interconnect resources of the programmable IC. A second subset of the second data is assigned to program a second type of configuration memory cells to implement the non-critical portion of the circuit design on a second subset of programmable logic resources and a second subset of programmable interconnect resources. The second data are stored in an electronically readable storage medium.

    Abstract translation: 为了在可编程集成电路（IC）上实现电路设计，生成用于实现电路设计的第一数据。 确定电路设计的关键部分和非关键部分，并且为可编程IC的编程配置存储器单元产生第二数据以实现电路设计。 分配第二数据的第一子集以编程第一类型的配置存储器单元，以在可编程逻辑资源的第一子集和可编程IC的可编程互连资源的第一子集上实现电路设计的关键部分。 分配第二数据的第二子集以编程第二类型的配置存储器单元，以在可编程逻辑资源的第二子集和可编程互连资源的第二子集上实现电路设计的非关键部分。 第二数据被存储在电子可读存储介质中。

    Electro-static discharge (ESD) damage self-test
    19.
    发明授权
    Electro-static discharge (ESD) damage self-test 有权

    公开(公告)号：US11177654B1

    公开(公告)日：2021-11-16

    申请号：US16152011

    申请日：2018-10-04

    Applicant: Xilinx, Inc.

    Inventor： John K. Jennings ,  James Karp ,  Michael J. Hart

    IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

    Abstract: Examples described herein provide a circuit and methods for self-testing to detect damage to a device, which damage may be caused by an Electro-Static Discharge (ESD) event. In an example, an integrated circuit includes an input/output circuit, an ESD protection circuit, and a system monitor. The input/output circuit has an input/output node. The ESD protection circuit is connected to the input/output node. The system monitor has a driving/measurement node selectively connectable to the input/output node. The system monitor is configured to drive and measure a voltage of the driving/measurement node. The system monitor is further configured to determine, based on driving and measuring the voltage of the driving/measurement node, whether a damaged device is present. The damaged device is in the input/output circuit or the ESD protection circuit.

    Single event latch-up (SEL) mitigation techniques
    20.
    发明授权
    Single event latch-up (SEL) mitigation techniques 有权

    公开(公告)号：US10811493B2

    公开(公告)日：2020-10-20

    申请号：US16109273

    申请日：2018-08-22

    Applicant: Xilinx, Inc.

    Inventor： James Karp ,  Michael J. Hart

    IPC: H01L29/06 ,  H01L27/092 ,  H01L27/06

    Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

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