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公开(公告)号：US11854617B2
公开(公告)日：2023-12-26
申请号：US18156707
申请日：2023-01-19
发明人： Hiroki Noguchi , Ku-Feng Lin
CPC分类号： G11C13/004 , G11C13/0026 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： A memory device is provided. The memory device includes several sense amplifiers and at least one reference cell. Each of the sense amplifiers has a first terminal and a second terminal. The first terminals of the sense amplifiers are coupled to a memory cell block, and the second terminals of the sense amplifiers are coupled together to transmit a read current. The at least one reference cell transmits the read current to a ground terminal. The at least one reference cell has a decreased resistance value when a number N of the sense amplifiers increases.
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公开(公告)号：US20230377629A1
公开(公告)日：2023-11-23
申请号：US18361559
申请日：2023-07-28
IPC分类号： G11C11/408 , G11C11/4096 , G11C11/4094
CPC分类号： G11C11/4087 , G11C11/4096 , G11C11/4094 , G11C11/4085
摘要： A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.
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公开(公告)号：US11762732B2
公开(公告)日：2023-09-19
申请号：US17556101
申请日：2021-12-20
发明人： Hiroki Noguchi , Yu-Der Chih , Hsueh-Chih Yang , Randy Osborne , Win San Khwa
CPC分类号： G06F11/102 , G11C11/1655 , G11C29/52
摘要： A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.
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公开(公告)号：US11742021B2
公开(公告)日：2023-08-29
申请号：US17815076
申请日：2022-07-26
发明人： Hiroki Noguchi , Yu-Der Chih , Yih Wang
CPC分类号： G11C13/0069 , G11C11/1675 , G11C11/2275 , G11C2013/0092
摘要： A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
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公开(公告)号：US11631440B2
公开(公告)日：2023-04-18
申请号：US17731248
申请日：2022-04-27
发明人： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
摘要： A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.
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公开(公告)号：US11605427B2
公开(公告)日：2023-03-14
申请号：US17140605
申请日：2021-01-04
发明人： Hiroki Noguchi , Yu-Der Chih , Yih Wang
摘要： A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
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公开(公告)号：US20220366982A1
公开(公告)日：2022-11-17
申请号：US17815076
申请日：2022-07-26
发明人： Hiroki Noguchi , Yu-Der Chih , Yih Wang
摘要： A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
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公开(公告)号：US20220336037A1
公开(公告)日：2022-10-20
申请号：US17856756
申请日：2022-07-01
发明人： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
摘要： A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.
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公开(公告)号：US20210272609A1
公开(公告)日：2021-09-02
申请号：US17118843
申请日：2020-12-11
发明人： Hiroki Noguchi
摘要： Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.
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公开(公告)号：US20240356562A1
公开(公告)日：2024-10-24
申请号：US18635948
申请日：2024-04-15
发明人： Win-San Khwa , Hiroki Noguchi , Ku-Feng Lin
CPC分类号： H03M7/16 , G11C11/1673 , H03K19/20
摘要： An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
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