公开(公告)号：US11699621B2

公开(公告)日：2023-07-11

申请号：US17521374

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Yu Lee ,  Huicheng Chang ,  Che-Hao Chang ,  Ching-Hwanq Su ,  Weng Chang ,  Xiong-Fei Yu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/823857 ,  H01L21/823821 ,  H01L27/0924 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/3115 ,  H01L21/31111

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

公开(公告)号：US20220367688A1

公开(公告)日：2022-11-17

申请号：US17874286

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

公开(公告)号：US20220367263A1

公开(公告)日：2022-11-17

申请号：US17869462

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsueh Wen Tsau ,  Chia-Ching Lee ,  Cheng-Lung Hung ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

公开(公告)号：US20220216201A1

公开(公告)日：2022-07-07

申请号：US17656295

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/11 ,  H01L29/06

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US20220059412A1

公开(公告)日：2022-02-24

申请号：US17521374

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Yu Lee ,  Huicheng Chang ,  Che-Hao Chang ,  Ching-Hwanq Su ,  Weng Chang ,  Xiong-Fei Yu

IPC: H01L21/8238 ,  H01L27/092

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

公开(公告)号：US11171061B2

公开(公告)日：2021-11-09

申请号：US16569820

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Yu Lee ,  Huicheng Chang ,  Che-Hao Chang ,  Ching-Hwanq Su ,  Weng Chang ,  Xiong-Fei Yu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

公开(公告)号：US20210134799A1

公开(公告)日：2021-05-06

申请号：US17120921

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L27/092 ,  H01L21/324 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/321 ,  H01L21/027

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

公开(公告)号：US20210043772A1

公开(公告)日：2021-02-11

申请号：US17077383

申请日：2020-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

公开(公告)号：US20210028290A1

公开(公告)日：2021-01-28

申请号：US16692571

申请日：2019-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pohan Kung ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

公开(公告)号：US20200083115A1

公开(公告)日：2020-03-12

申请号：US16686365

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Yu Lee ,  Huicheng Chang ,  Che-Hao Chang ,  Ching-Hwanq Su ,  Weng Chang ,  Xiong-Fei Yu

IPC: H01L21/8238 ,  H01L27/092

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.