公开(公告)号：US09419136B2

公开(公告)日：2016-08-16

申请号：US14252147

申请日：2014-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance.

Abstract translation: 本公开涉及具有外延源极和漏极区域的晶体管器件，其具有向外延沟道区域提供应力的位错应力存储（DSM）区域和相关联的形成方法。 晶体管器件具有设置在半导体衬底上的外延层，以及设置在外延层上的栅极结构。 沟道区域在位于栅极结构的相对侧的外延源极和漏极区域之间的栅极结构的下方延伸。 第一和第二位错应力记忆（DSM）区域具有在沟道区域内产生应力的应力晶格。 第一和第二DSM区域分别从外延源区域的下面延伸到外延源区域内的从外延漏极区域下方的第一位置到外延漏极区域内的第二位置。 使用第一和第二DSM区域来压缩通道区域，提高了设备​​性能。

公开(公告)号：US20150243759A1

公开(公告)日：2015-08-27

申请号：US14222759

申请日：2014-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Syuan Huang ,  Tsung-Hsing Yu ,  Yi-Ming Sheu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for improving analog gain in long channel devices associated with a semiconductor workpiece is provided. A gate oxide layer is formed on the semiconductor workpiece, and a plurality of gate structures are formed over the gate oxide layer, wherein a first pair of the plurality of gate structures define a short channel device region and a second pair of the plurality of gate structures define a long channel device region. A first ion implantation with a first dopant is performed at a first angle, wherein the first dopant is one of an n-type dopant and a p-type dopant. A second ion implantation with a second dopant is performed at a second angle, wherein the second angle is greater than the first angle. The second dopant is one or an n-type dopant and a p-type dopant that is opposite of the first dopant, and a height of the plurality of gate structures and the second angle generally prevents the second ion implantation from implanting ions into the short channel device region.

Abstract translation: 提供了一种用于改善与半导体工件相关联的长通道器件中的模拟增益的方法。 在半导体工件上形成栅极氧化层，并且在栅极氧化物层上形成多个栅极结构，其中多个栅极结构中的第一对限定短沟道器件区域和第二对多个栅极 结构定义了一个长通道器件区域。 以第一角度执行具有第一掺杂剂的第一离子注入，其中第一掺杂剂是n型掺杂剂和p型掺杂剂之一。 以第二角度执行具有第二掺杂剂的第二离子注入，其中第二角度大于第一角度。 第二掺杂剂是与第一掺杂剂相反的一种或n型掺杂剂和p型掺杂剂，并且多个栅极结构的高度和第二角度通常防止第二离子注入将离子注入到短路中 通道设备区域。

公开(公告)号：US11145762B2

公开(公告)日：2021-10-12

申请号：US16016748

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US10276717B2

公开(公告)日：2019-04-30

申请号：US15247024

申请日：2016-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

公开(公告)号：US20150162445A1

公开(公告)日：2015-06-11

申请号：US14100263

申请日：2013-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。

公开(公告)号：US11955554B2

公开(公告)日：2024-04-09

申请号：US17812997

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/7848

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

公开(公告)号：US10516047B2

公开(公告)日：2019-12-24

申请号：US15471318

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Charles Chew-Yuen Young ,  Yi-Ming Sheu ,  Chun-Fu Cheng ,  Yi-Han Wang

IPC: H01L29/775 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/417 ,  H01L29/423

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.

公开(公告)号：US20190245089A1

公开(公告)日：2019-08-08

申请号：US16390373

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.

公开(公告)号：US09899517B2

公开(公告)日：2018-02-20

申请号：US15345814

申请日：2016-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/24 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.

公开(公告)号：US20160365447A1

公开(公告)日：2016-12-15

申请号：US15247024

申请日：2016-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。