公开(公告)号：US10529863B2

公开(公告)日：2020-01-07

申请号：US16230025

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Cheng-Wei Chen ,  Shiu-Ko Jangjian ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

公开(公告)号：US10164095B2

公开(公告)日：2018-12-25

申请号：US14805450

申请日：2015-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Ting-Chun Wang ,  Wei-Ming You ,  J. W. Wu

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.

公开(公告)号：US09589804B2

公开(公告)日：2017-03-07

申请号：US14814370

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Shiu-Ko Jangjian ,  Chung-Ren Sun ,  Ming-Te Chen ,  Ting-Chun Wang ,  Jun-Jie Cheng

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.

Abstract translation: 半导体器件包括半导体鳍片，衬里氧化物层，氮化硅基层和栅极氧化物层。 半导体翅片具有顶表面，与顶表面相邻的第一侧表面，以及设置在第一侧表面下方并与其邻近的第二侧表面。 衬里氧化物层周边地包围半导体鳍片的第二侧表面。 氮化硅基层与衬里氧化物层一致地设置。 栅极氧化物层与顶表面和第一侧表面共形设置。

公开(公告)号：US11031488B2

公开(公告)日：2021-06-08

申请号：US16852973

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko Jangjian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L21/285 ,  H01L29/49 ,  H01L29/165

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.

公开(公告)号：US10886226B2

公开(公告)日：2021-01-05

申请号：US16050191

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko JangJian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L23/532 ,  H01L29/417 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

公开(公告)号：US10141413B2

公开(公告)日：2018-11-27

申请号：US14745600

申请日：2015-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Che Huang ,  Pu-Fang Chen ,  Ting-Chun Wang

IPC: H01L31/0232 ,  H01L29/32 ,  H01L29/16 ,  H01L21/67 ,  H01L21/66 ,  H01L21/322 ,  H01L21/324 ,  C30B29/06

Abstract: Some embodiments relate to a silicon wafer having a disc-like silicon body. The wafer includes a central portion circumscribed by a circumferential edge region. A plurality of sampling locations, which are arranged in the circumferential edge region, have a plurality of wafer property values, respectively, which correspond to a wafer property. The plurality of wafer property values differ from one another according to a pre-determined statistical edge region profile.

公开(公告)号：US10026838B2

公开(公告)日：2018-07-17

申请号：US15054086

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yung-Yu Wang ,  Yung-Hsiang Chan ,  Chia-Ying Tsai ,  Ting-Chun Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.

公开(公告)号：US09728646B2

公开(公告)日：2017-08-08

申请号：US14925846

申请日：2015-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Shiu-Ko Jangjian ,  Cheng-Wei Chen ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7854 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment.

公开(公告)号：US09478660B2

公开(公告)日：2016-10-25

申请号：US14677405

申请日：2015-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Shiu-Ko Jangjian ,  Chi-Cherng Jeng ,  Chih-Nan Wu ,  Chun-Che Lin ,  Ting-Chun Wang

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract translation: 提供了一种翅片场设备结构及其形成方法。 FinFET器件结构包括从衬底延伸的衬底和鳍结构。 FinFET器件结构还包括形成在衬底上的隔离结构。 翅片结构具有顶部和底部，并且底部嵌入隔离结构中。 FinFET器件结构还包括形成在鳍结构的顶部上的保护层。 界面处于保护层和翅片结构的顶部之间，并且界面的粗糙度在约0.1nm至约2.0nm的范围内。

公开(公告)号：US20140273291A1

公开(公告)日：2014-09-18

申请号：US13889515

申请日：2013-05-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Che Huang ,  Pu-Fang Chen ,  Ting-Chun Wang

IPC: H01L21/66

CPC classification number: H01L21/3225 ,  C30B29/06 ,  H01L21/324 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing.

Abstract translation: 提供了一种用于限定半导体晶片以进行后续处理（诸如热处理）的方法。 围绕半导体晶片的周边限定多个位置，并且在多个位置的每一个处测量一个或多个特性，例如存在的氧浓度和体积微缺陷的密度。 基于在多个位置处测量的一个或多个属性来确定与半导体晶片的外围相关联的统计概况。 当统计特性落在预定范围内时，半导体晶片随后进行热处理。 当统计概况偏离预定范围时，半导体晶片从后续处理中被拒绝。 因此，容易发生变形，翘曲和断裂的晶片从随后的热处理中被拒绝。