公开(公告)号：US20170229372A1

公开(公告)日：2017-08-10

申请号：US15016886

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/3736 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the dielectric layer, and the conductive feature includes a catalyst layer and a conductive element. The catalyst layer is between the conductive element and the dielectric layer, and the catalyst layer is in physical contact with the conductive element. The catalyst layer continuously surrounds a sidewall and a bottom of the conductive element. The catalyst layer is made of a material different from that of the conductive element, and the catalyst layer is capable of lowering a formation temperature of the conductive element.

公开(公告)号：US20240266211A1

公开(公告)日：2024-08-08

申请号：US18618044

申请日：2024-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0228 ,  H01L21/30604 ,  H01L21/31116

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

公开(公告)号：US20220310442A1

公开(公告)日：2022-09-29

申请号：US17806726

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chin LEE ,  Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L21/02

Abstract: A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

公开(公告)号：US20190096801A1

公开(公告)日：2019-03-28

申请号：US15715327

申请日：2017-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a substrate, a dielectric layer, a via, a line, and a capping layer. The substrate includes at least one conductive layer, in which a top surface of the at least one conductive layer has a first portion and a second portion. The dielectric layer is disposed on the substrate and the first portion of the top surface of the at least one conductive layer. The via is disposed in the dielectric layer on the second portion of the top surface of the at least one conductive layer. The line is disposed on the via and a portion of the dielectric layer. The capping layer is disposed on a top surface of the line and peripherally encloses a side surface of the line, in which the capping layer has an etch selectivity with respect to the line.

公开(公告)号：US20170140982A1

公开(公告)日：2017-05-18

申请号：US14942386

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen TIEN ,  Carlos H. DIAZ ,  Chung-Ju LEE ,  Shau-Lin SHUE ,  Tien-I BAO

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/311 ,  H01L21/288

CPC classification number: H01L21/7688 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2221/1063

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material.

公开(公告)号：US20240321573A1

公开(公告)日：2024-09-26

申请号：US18678463

申请日：2024-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan LEE ,  Yung-Hsu WU ,  Cheng-Chin LEE ,  Hai-Ching CHEN ,  Hsin-Yen HUANG ,  Shau-Lin SHUE

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/02304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US20240274528A1

公开(公告)日：2024-08-15

申请号：US18641745

申请日：2024-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252

Abstract: An interconnect structure includes a via including a first barrier layer and a bulk layer disposed over the first barrier layer, and a conductive line disposed over a top surface of the via. The conductive line includes a conductive layer disposed over a top surface of the bulk layer, and a second barrier layer disposed on sidewalls of the conductive layer. The interconnect structure is free of a nitride layer between the bulk layer and the conductive layer.

公开(公告)号：US20200020580A1

公开(公告)日：2020-01-16

申请号：US16035455

申请日：2018-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Chin LEE ,  Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105

Abstract: A method for forming a semiconductor structure is provided. A substrate including a metal portion and a low-k dielectric portion formed thereon is provided. The metal portion adjoins the low-k dielectric portion. A SAM solution is prepared. The SAM solution includes at least one blocking compound and a multi-solvent system. The multi-solvent system includes an alcohol and an ester. The SAM solution is applied over surfaces of the metal portion and the low-k dielectric portion. The substrate is heated to remove the multi-solvent system of the SAM solution to form a blocking layer on one of the metal portion and the low-k dielectric portion. A material layer is selectively deposited on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil. The blocking layer is removed from the substrate.

公开(公告)号：US20200006116A1

公开(公告)日：2020-01-02

申请号：US16270057

申请日：2019-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan LEE ,  Cheng-Chin Lee ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

公开(公告)号：US20180350741A1

公开(公告)日：2018-12-06

申请号：US16048921

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/8234

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.