公开(公告)号：US20200020744A1

公开(公告)日：2020-01-16

申请号：US16583116

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Kuo-Ching Huang ,  Tong-Chern Ong

IPC: H01L27/24 ,  H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may include forming a control device within a substrate. A first plurality of interconnect layers are formed within a first inter-level dielectric (ILD) structure over the substrate. A first memory device and a second memory device are formed over the first ILD structure. A second plurality of interconnect layers are formed within a second ILD structure over the first ILD structure. The first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device.

公开(公告)号：US09991368B2

公开(公告)日：2018-06-05

申请号：US15371801

申请日：2016-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L27/00 ,  H01L29/732 ,  H01L29/66 ,  H01L27/22 ,  H01L27/24 ,  G11C11/16 ,  G11C13/00

CPC classification number: H01L29/732 ,  G11C11/161 ,  G11C11/40 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2454 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/82 ,  H01L45/04

Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

公开(公告)号：US20170062525A1

公开(公告)日：2017-03-02

申请号：US15347255

申请日：2016-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Ting ,  Chi-Wen Liu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L27/24 ,  H01L29/78 ,  H01L29/423 ,  H01L27/22

CPC classification number: H01L27/2454 ,  H01L27/228 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments of the present disclosure relate to an integrated chip having a vertical transistor device. The integrated chip may have a semiconductor body with a trench extending along first sides of a source region, a channel region over the source region, and a drain region over the channel region. A gate electrode is arranged along a first sidewall of the trench, and a metal contact is arranged on the drain region. An isolation dielectric material is disposed within the trench. The isolation dielectric material is vertically over a top surface of the gate electrode and is laterally adjacent to the gate electrode.

Abstract translation: 本公开的一些实施例涉及具有垂直晶体管器件的集成芯片。 集成芯片可以具有半导体本体，其具有沿源区域的第一侧延伸的沟槽，源极区域上的沟道区域以及沟道区域上的漏极区域。 栅电极沿着沟槽的第一侧壁布置，并且漏极区域上布置有金属接触。 隔离电介质材料设置在沟槽内。 隔离电介质材料垂直于栅电极的顶表面并且横向邻近栅电极。

公开(公告)号：US09153672B2

公开(公告)日：2015-10-06

申请号：US13723762

申请日：2012-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: G11C7/00 ,  H01L29/732 ,  G11C11/40 ,  H01L29/82 ,  H01L45/00 ,  H01L29/66 ,  G11C13/00 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L29/732 ,  G11C11/161 ,  G11C11/40 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2454 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/82 ,  H01L45/04

Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

Abstract translation: 本公开的一些方面涉及存储器设备。 存储器件包括具有第一导电类型并且耦合到存储器件的源极线的集电极区域。 基极区域形成在集电极区域上并且具有第二导电类型。 栅极结构耦合到基极区域并用作存储器件的第一和第二相邻存储器单元的共享字线。 第一和第二发射极区域形成在基极区域上并且具有第一导电类型。 第一和第二发射极区域布置在栅极结构的相对侧上。 第一和第二触点分别从第一和第二发射极区域向上延伸，并分别将第一和第二发射极区域分别耦合到第一和第二相邻存储器单元的第一和第二数据存储元件。

公开(公告)号：US11594632B2

公开(公告)日：2023-02-28

申请号：US17117711

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mickey Hsieh ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Kuo-Chi Tu ,  Pili Huang ,  Cheng-Jun Wu ,  Chao-Yang Chen

IPC: H01L29/78 ,  H01L27/11507 ,  H01L49/02 ,  H01L29/66 ,  H01L29/51 ,  H01L27/1159 ,  H01L21/28

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

公开(公告)号：US11315931B2

公开(公告)日：2022-04-26

申请号：US16942197

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/762 ,  H01L29/06

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

公开(公告)号：US10985316B2

公开(公告)日：2021-04-20

申请号：US16359092

申请日：2019-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Pili Huang ,  Cheng-Jun Wu

IPC: H01L27/088 ,  H01L21/8236 ,  H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnect layers. A lower surface of the bottom electrode includes a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reducing layer contacts the lower surface of the bottom electrode. The reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.

公开(公告)号：US20170033161A1

公开(公告)日：2017-02-02

申请号：US15292334

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

CPC classification number: H01L27/2463 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

Abstract translation: 一些实施例涉及包括设置在半导体衬底上的存储器单元阵列的集成电路器件。 第一金属线阵列被布置在衬底上的第一高度处并连接到阵列的存储器单元。 每个第一金属线具有第一横截面积。 第二金属线阵列设置在衬底上的第二高度处，并连接到阵列的存储单元。 每个第二金属线具有大于第一横截面积的第二横截面积。

公开(公告)号：US20150187418A1

公开(公告)日：2015-07-02

申请号：US14152244

申请日：2014-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: G11C13/00 ,  H01L27/24

CPC classification number: H01L27/2463 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes an array of RRAM cells, an array of bit lines for the array of RRAM cells, and an array of source lines for the array of RRAM cells. Both the source lines and the bit lines are in metal interconnect layers above the RRAM cells. The source line are thereby provided with a higher than conventional wire size, which increases the reset speed by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device are consequentially improved to a similar degree.

Abstract translation: 集成电路设备包括RRAM单元阵列，RRAM单元阵列的位线阵列，以及RRAM单元阵列的源极阵列。 源极线和位线都位于RRAM单元上方的金属互连层中。 因此，源极线被提供有高于常规电线尺寸，其将复位速度提高约一个数量级。 RRAM晶体管的寿命和RRAM器件的耐用性因此相应地得到改善。

公开(公告)号：US11696521B2

公开(公告)日：2023-07-04

申请号：US16939497

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Cheng-Jun Wu

IPC: H01L45/00 ,  H10N70/00 ,  G11C13/00 ,  H10B63/00

CPC classification number: H10N70/883 ,  G11C13/0007 ,  H10B63/00 ,  H10N70/021 ,  H10N70/841

Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.