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    RRAM-based monotonic counter
    11.
    发明授权
    RRAM-based monotonic counter 有权

    公开(公告)号：US10482958B2

    公开(公告)日：2019-11-19

    申请号：US15898119

    申请日：2018-02-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Lien Linus Lu ,  Yu-Der Chih ,  Chung-Cheng Chou ,  Tong-Chern Ong

    IPC: G11C13/00 ,  G06F21/64 ,  G06F12/14 ,  G06F21/79 ,  G11C7/24

    Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state; and a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state.

    Operating resistive memory cell
    13.
    发明授权
    Operating resistive memory cell 有权
    工作电阻式存储单元

    公开(公告)号：US09196360B2

    公开(公告)日：2015-11-24

    申请号：US14161193

    申请日：2014-01-22

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Chung-Cheng Chou ,  Yue-Der Chih

    IPC: G11C13/00 ,  H03K17/56 ,  G11C11/56

    CPC classification number: G11C13/0064 ,  G11C11/56 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2213/79 ,  H03K17/56

    Abstract: A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source.

    Abstract translation: 公开了一种包括电流源和电流比较器的电路。 电流源连接到电阻存储器单元以产生驱动电流。 电流比较器具有连接到电流源和电阻存储器单元的感测节点，以感测通过感测节点注入到电流比较器的注入电流，其中当电阻性存储器单元的电阻状态切换使得电流比较器确定 注入电流的量增加到超过或者减小到达阈值时，电流比较器关闭电流源。

    Resistive memory device with trimmable driver and sinker and method of operations thereof
    14.
    发明授权
    Resistive memory device with trimmable driver and sinker and method of operations thereof 有权

    公开(公告)号：US11423982B2

    公开(公告)日：2022-08-23

    申请号：US16932736

    申请日：2020-07-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Cheng Chou

    IPC: G11C8/00 ,  G11C13/00 ,  G11C11/16

    Abstract: A device is disclosed. The device includes a first memory cell, a second memory cell, a first pair of a driver and a sinker, and a second pair of a driver and a sinker. The first memory cell is coupled between the first pair of the driver and the sinker through a first line and a second line. The second memory cell is coupled between the second pair of the driver and the sinker through a third line and a fourth line. The first pair of the driver and the sinker are configured to be controlled to have resistances depending on a row location of the first memory cell in a memory column.

    Resistive random access memory device
    15.
    发明授权
    Resistive random access memory device 有权

    公开(公告)号：US11024381B2

    公开(公告)日：2021-06-01

    申请号：US17003761

    申请日：2020-08-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der Chih ,  Chung-Cheng Chou ,  Wen-Ting Chu

    IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

    RESISTIVE RANDOM ACCESS MEMORY DEVICE
    16.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICE 审中-公开

    公开(公告)号：US20190164606A1

    公开(公告)日：2019-05-30

    申请号：US16158498

    申请日：2018-10-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Chung-Cheng Chou ,  Wen-Ting Chu

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

    Fast sense amplifier with bit-line pre-charging
    19.
    发明授权
    Fast sense amplifier with bit-line pre-charging 有权

    公开(公告)号：US09812198B1

    公开(公告)日：2017-11-07

    申请号：US15416191

    申请日：2017-01-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Cheng Chou

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C13/0026 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054

    Abstract: A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.

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